RISC-V at HotChips-26

The RISC-V team was out in force at the HotChips-26 conference manning a sponsor booth.

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Yunsup arrives early on Sunday to set up the RISC-V booth.

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Alongside a bunch of cool giveaways, including RISC-V buttons and bumper stickers, we had several demo boards at the conference. From left to right: a dual-core Rocket+Hwacha system in IBM’s 45nm SOI process, running up to 1.35GHz, a single core Rocket+Hwacha system in ST 28nm FDSOI process running down to 0.45V, and an FPGA prototype running on a Xilinx Zybo board.

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The Berkeley RISC-V team pose for a group shot at the end of the conference. From left to right: Steven Bailey, Henry Cook, Sagar Karandikar, Palmer Dabbelt, Krste Asanovic, Adam Izraelevitz, Colin Schmidt, Yunsup Lee, Andrew Waterman, Brian Zimmer, Scott Beamer, David Patterson.

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