The RISC-V Privileged Architecture Draft Specification has been released and is available at: /specifications/privileged-isa/.
This is only a proposal at this point, and we welcome community feedback and comments on this draft. Please participate in the discussion on the public sw-dev and hw-dev RISC-V mailing lists, to which you can subscribe on the www.riscv.org website. We hope to freeze the core parts of this privileged architecture specification later this year.
We will very shortly be releasing an updated Spike simulator and Linux port conforming to the proposed standard, along with QEMU updates to follow. Stay tuned for announcements.
Please use the following citation for this document.
A. Waterman, Y. Lee, R. Avizienis, D. A. Patterson, and K. Asanović, “The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.7,” EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-49, May 2015.