Preliminary Agenda for the 2nd RISC-V Workshop is Posted!

The preliminary agenda for the 2nd RISC-V workshop is posted here.

Thanks to the RISC-V community for submitting interesting talk proposals, we have a great program covering a broad range of exciting topics including: updates from many RISC-V projects around the globe; tiny RISC-V processors, out-of-order RISC-V processors, multi-core RISC-V processors, clockless RISC-V processors; 28nm RISC-V prototypes; verification; RISC-V privileged, compressed, vector extension proposals.

We look forward to seeing you all in Berkeley for an engaging workshop!

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