RISC-V in Verilog

V-scale, an implementation of an RV32IM core in Verilog has been released and is available at: https://github.com/ucb-bar/vscale.

This core implements a simple, Z-scale-class pipeline, and is designed for integration with either existing microcontroller-class bus interconnects or the Rocket chip generator. The build infrastructure for both flows will be publicly released with an upcoming update to the platform of small RISC-V systems compatible with Z-scale.

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