4th RISC-V Workshop Proceedings

Our 4th RISC-V Workshop was hosted at MIT in Cambridge, MA, this past July 12-13, 2016. The Workshop agenda is shown below together with slides and videos from each of the talks.  We had tremendous participation with 266 registered attendees representing 63 companies and 42 universities from around the world.

About the Workshop

The goals for our RISC-V workshops are for the community to share information about recent activity in various RISC-V projects underway around the globe, and to build consensus on future steps with the RISC-V ISA. This workshop features talks and poster presentations conveying recent activity in the RISC-V community at large, collected during an open submission period.


Tuesday, July 12th, 2016

Time Event Speaker, Affiliation Media
8:00am Networking Breakfast
8:30am Workshop Logistics and RISC-V Foundation Update Rick O’Connor, RISC-V Slides | Video
9:00am RISC-V Interrupts Krste Asanović, UC Berkeley & SiFive Inc. Slides | Video
9:30am Formal Specification of RISC-V Uniprocessor Consistency Arvind, MIT Slides | Video
10:00am Heterogeneous Multicore RISC-V Processors in FD-SOI Silicon Thomas Peyret, CEA Tech Slides | Video
10:30am Networking Break
11:00am NVIDIA RISC-V Evaluation Story Joe Xie, NVIDIA Slides | Video
11:30am ISA Shootout – a Comparison of RISC-V, ARM, and x86 Chris Celio, UC Berkeley Slides | Video
12:00pm Trace Debugging in lowRISC Wei Song, University of Cambridge Slides | Video
12:30pm Networking Lunch
1:30pm RISC-V I/O Scale Out Architecture for Distributed Data Analytics Mohammad Akhter, IDT Slides | Video
2:00pm Coherent Storage: Brave New World of Non-Volatile Main Memory Dejan Vucinić, Western Digital Slides | Video
2:30pm RISC-V as basis for ASIP Design – an IoT Security Example Dan Ganousis, Codasip Drake Smith, Secure RF Slides | Video
3:00pm An Update on Building the RISC-V Software Ecosystem Arun Thomas, BAE Systems Slides | Video
3:15pm ORCA-LVE: Embedded RISC-V with Lightweight Vector Extensions Guy Lemieux, VectorBlox Slides | Video
3:30pm Networking Break & Breakout Sessions
4:00pm FPGArduino: A Cross-Platform RISC-V IDE for masses Marko Zec, University of Zagreb Slides | Video
4:15pm SiFive’s RISC-V computer: An open software development platform for RISC-V SoCs Jack Kang, SiFive Slides | Video
4:30pm 18 Poster / Demo Previews ~ 3min per presenter Slides | Video
5:30pm Leave to walk over to the Google facility at 355 Main St.
6:00pm Networking Reception, Posters Sessions & Demos Hosted at Google, 355 Main St.
8:00pm Adjourn for the Day

Wednesday, July 13th, 2016

Time Event Speaker, Affiliation Media
8:00am Networking Breakfast
8:30am Riscy Processors – A Collection of Open-Sourced RISC-V Processors Andy Wright, MIT Slides | Video
9:00am SW Programmable FPGA IoT Platform: RISC-V Processor with Auto-Generated HW Accelerators Andrew Canis, LegUp Computing Slides | Video
9:30am Apache Mynewt: The Next Great Open Source OS for 32-Bit MCUs. Coming soon to a RISC-V MCU near you! James Pace, Runtime Slides | Video
10:00am DSP ISA Extensions for an Open-Source RISC-V Implementation Pasquale Davide Schiavone, ETH Zurich Slides | Video
10:15am The DOVER Edge: A Metadata-Enhanced RISC-V Architecture Andre DeHon, DRAPER Labs Slides | Video
10:30am Networking Break
11:00am Improving The Performance Per Area Factor of RISC-V Based Multi-Core Systems Tobias Strauch, EDAptix Slides | Video
11:15am Working Towards a Debian RISC-V Port Manuel A. Fernandez Montecelo Slides | Video
11:30am Kami: A Framework for RISC-V HW Verification Murali Vijayaraghavan, MIT Slides | Video
11:45pm 4th RISC-V Workshop Wrap Up Rick O’Connor, RISC-V Foundation no slides | Video
12:00pm Networking Lunch (Workshop Ends)