5th RISC-V Workshop Proceedings

5th RISC-V Workshop Proceedings November 29-30, 2016

 

GoogleQuad1

RISC-V logo

 

 

google

Proceedings for the 5th RISC-V Workshop, hosted at Google’s Quad campus in Mountain View, California on November 29-30, 2016 are now available with links to the slide presentations and videos shown in the Agenda below.

The goals of the workshop are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of the instruction set.

Each workshop has helped both document the rapidly rising popularity of RISC-V and boosted it further due to the information shared and collaborations formed at the event.

In case you missed the event, here’s some coverage of the workshop to help bring you up to speed:

Please be sure to join us for the 6th RISC-V Workshop hosted by NVIDIA and Shanghai Jiao Yong University in Shanghai China, May 9th-10th, 2017.

Hope to see you at the next workshop!

5th RISC-V Workshop Proceedings

Tuesday, November 29th, 2016

Time Event Speaker, Affiliation Media
8:00am Networking Breakfast
8:45am 5th RISC-V Workshop Introduction Rick O’Connor, RISC-V; Dom Rizzo, Google Slides | Video
9:00am RISC-V @ UC San Diego Michael B. Taylor, UC San Diego Slides | Video
9:15am Updates on PULPino Florian Zaruba, ETH Zurich Slides | Video
9:30am SiFive FE300 and low-cost HiFive Development Board Jack Kang, SiFive Slides | Video
10:00am Rapid silicon prototyping and production for RISC-V SoCs Neil Hand, Codasip Slides | Video
10:30am Networking Break
11:00am Extending RISC-V for Application-Specific Requirements Steve Cox, Synopsys Slides | Video
11:30am A memory model for RISC-V Muralidaran Vijayaraghavan, MIT Slides | Video
12:00pm A Memory Consistency Model for RISC-V Caroline Trippel, Princeton University Slides | Video
12:30pm Networking Lunch
1:30pm Keynote Address: Trust, Transparency and Simplicity Eric Grosse, Google Slides | Video
2:00pm RISC-V Foundation Update Rick O’Connor, RISC-V Foundation Slides | Video
2:15pm RISC-V Marketing Committee Update Arun Thomas, BAE Systems Slides | Video
2:30pm RISC-V Technical Committee Update Yunsup Lee, SiFive Slides | Video
2:45pm Rocket Chip Project: a nonprofit foundation for hosting open-source RISC-V implementations, tools, code Yunsup Lee, SiFive Slides | Video
3:00pm Networking Break
3:30pm 128-bit addressing in RISC-V and security Steve Wallach, Micron Slides | Video
4:00pm The Challenges of Securing and Authenticating Embedded Devices and a Suggested Approach for RISC-V Derek Atkins, SecureRF Slides | Video
4:15pm Sanctum: Minimal Hardware Extensions for Strong Software Isolation Ilia Lebedev, MIT Slides | Video
4:45pm Joined up debugging and analysis in the RISC-V world Gajinder Panesar, UltraSoC Slides | Video
5:15pm Poster / Demo Previews ~ 2min per presenter Slides | Video
5:45pm Transition to Reception
6:00pm Networking Reception, Posters Sessions and Demos Hosted by Google at the Computer History Museum
9:00pm Adjourn for the Day

Wednesday, November 30th, 2016

Time Event Speaker, Affiliation Media
8:00am Networking Breakfast
9:00am OpenSoC System Architect: An Open Toolkit for Building High Performance SoCs Farzad Fatollahi-Fard, Lawrence Berkeley National Lab Slides | Video
9:30am “V” Vector Extension Proposal Krste Asanovic, UC Berkeley & SiFive Slides | Video
10:00am Towards Thousand-Core RISC-V Shared Memory Systems Quan Nguyen,MIT Slides | Video
10:15am SCRx: a family of state-of-the art RISC-V synthesizable cores Alexander Redkin, Syntacore Slides | Video
10:30am Networking Break
11:00am Enabling hardware/software co-design with RISC-V and LLVM Alex Bradbury, lowRISC Slides | Video
11:30am VM threads: an alternative model for virtual machines on RISC-V Ron Minnich, Google Slides | Video
12:00pm Enabling low-power, smartphone-like graphical UIs for RISC-V SoCs Michael Gielda, Antmicro Slides | Video
12:30pm Networking Lunch
1:30pm A Fast Instruction Set Simulator for RISC-V Maxim Maslov, Esperanto Slides | Video
2:00pm Go on RISC-V Benjamin Barenblat, Michael Pratt, Google Slides | Video
2:15pm A Java Virtual Machine for RISC-V: Porting the Jikes RVM Martin Maas, UC Berkeley Slides | Video
2:30pm YoPuzzle: A mRISC-V development platform for next generations Elkim Roa, Universidad Industrial de Santander Slides | Video
2:45pm RISC-V Community needs Peripheral Cores Elkim Roa, Universidad Industrial de Santander Slides | Video
3:00pm Networking Break
3:30pm Sub-microsecond Adaptive Voltage Scaling in a 28nm RISC-V SoC Ben Keller, UC Berkeley Slides | Video
4:00pm Reprogrammable Redundancy for Cache Vmin Reduction in a 28nm RISC-V Processor Brian Zimmer, UC Berkeley; NVIDIA Slides | Video
4:30pm 5th RISC-V Workshop Conclusion Rick O’Connor, RISC-V Foundation; Dom Rizzo, Google Video
4:45pm End of Workshop
Tags: