RISC-V chosen as Best Technology of 2016

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The Linley Group Announces Winners of Annual Analysts’ Choice Awards

 

 

 

In a news release issued today, January 12th, 2017, The Linley Group today announced the winners of its annual Analysts’ Choice Awards which recognize the top semiconductor products of 2016 in seven categories: embedded processors, mobile processors, server processors, processor-IP cores, mobile chip, networking chip, and best technology.  The RISC-V Instruction Set Architecture was selected as the Best Technology of 2016.

In support of the RISC-V ISA, Linley Gwennap, Principal Analyst, The Linley Group said: “RISC-V is a modern take on the classic RISC instruction set, providing a clean and extensible approach that is suitable for a broad range of microprocessor implementations. More significantly, the open-source, royalty-free RISC-V instruction set creates a new business model for CPU designers. This combination has generated sizeable industry interest in RISC-V, which will lead to several commercial deployments this year and beyond.”

Full details of The Linley Group Analysts’ Choice Awards are available in this edition of The Linley Group Microprocessor Report (MPR) with the RISC-V excerpt shown below.

RISC-V Chosen as Best Technology
 of 2016

The RISC-V (“risk-five”) instruction-set architecture wins our Best Technology Award. Krste Asanovic, Andrew Waterman, and Yunsup Lee developed the open-source ISA at UC Berkeley, with input from David Patterson. RISC-V is a general-purpose ISA that’s extensible and royalty free. It’s clean and modular with a 32-, 64-, or 128-bit integer base and various optional extensions (e.g., floating point). The RISC-V Foundation aims to proliferate the ISA and develop the broad software support of commercial ISAs such as the x86 and ARM. If successful, it will be the Linux of microprocessor architectures (see MPR 3/28/16, “RISC-V Offers Simple, Modular ISA”). RISC-V is flexible enough to serve all markets, from MCUs to server processors. Implementations vary, from FPGAs to synthesized macros to fully custom layouts. It’s extensible, so designers can customize it for special-purpose workloads. The RISC-V Foundation manages the standard, creates compliance tests, and organizes the community. The ISA has attracted support from industry leaders such as Google and Oracle as well as academic partners. Several open-source RISC-V cores are freely available online. The first RISC-V startup is SiFive, which develops customer-specific SoCs using open-source CPU designs (see MPR 8/1/16, “SiFive Offers RISC-V Platforms”). We considered five other nominees for Best Technology. Bluetooth 5 improves the popular wireless standard to enable more types of devices to transfer greater amounts of data over longer distances. CCIX (pronounced “see-six”) is a new open standard for memory-coherent interconnects that will enable chip designers to develop more-powerful homogeneous and heterogeneous multicore processors. FD-SOI greatly reduces leakage current compared with standard bulk-CMOS transistors. High Bandwidth Memory 2 (HBM2) increases memory capacity and bandwidth, adds ECC support, and improves memory-controller efficiency. MulteFire is a proposed standard that would allow LTE cellular traffic to operate exclusively in unlicensed RF spectrum, enabling small-cell base stations to provide local service in new ways. 


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