6th RISC-V Workshop Agenda

6th RISC-V Workshop Agenda May 8-11, 2017

RISC-V logo

The preliminary agenda for the 6th RISC-V Workshop, co-hosted by NVIDIA and the Shanghai Jiao Tong University (SJTU) in Shanghai China on May 8-11, 2017 is shown below.  As with past workshops, our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of the instruction set.

This will be a four day event broken down as follow:

  • Monday May 8, 2017 – Introduction to RISC-V – this day long session is intended for those who are new to RISC-V and have yet to be exposed to the RISC-V ISA.  The session will consist of presentations from the RISC-V Foundation, some of the original creators of the RISC-V ISA and product presentations from vendors within the RISC-V community.
  • Tuesday and Wednesday May 9-10, 2017 – These two days will follow our traditional two day format with presentations covering various RISC-V projects underway within the RISC-V community and will include a poster / demo reception on Tuesday evening.
  • Thursday May 11, 2017 – The workshop week will conclude with RISC-V Foundation meetings with attendance restricted to members of the RISC-V Foundation.  The day will consist of Technical and Marketing Committee face to face meetings to progress the work currently underway within our various Task Groups.

Each workshop has helped both document the rapidly rising popularity of RISC-V and boosted it further due to the information shared and collaborations formed at the event. Please join us!

Workshop registration details can be found here. For attendees travelling from outside the Shanghai area, please be sure to say at the recommended hotel shown below as we will be providing a shuttle bus service from the hotel to the SJTU campus.

Recommended Hotel: Chateau Star River Shanghai Minhang

Preliminary Agenda

Monday, May 8th, 2017 Introduction To RISC-V

Time Event Speaker, Affiliation Media
8:00am Registration and Networking Breakfast
9:00am RISC-V Introduction – Opening Remarks Rick O’Connor, Executive Director, RISC-V Foundation
9:15am History of Computer Architecture and RISC Dave Patterson, Pardee Professor of Computer Science, Emeritus, UC Berkeley and author of “Computer Architecture: A Quantitative Approach”
10:15am Networking Break
10:45am Why RISC-V? “Instruction Sets Want to be Free” Krste Asanovic, Professor UC Berkeley, Chairman RISC-V Foundation, Co-Founder SiFive
11:45am Introduction to the RISC-V Foundation Rick O’Connor, Executive Director, RISC-V Foundation
12:15pm Morning Session Wrap UP Rick O’Connor, Executive Director, RISC-V Foundation
12:30pm Networking Lunch
1:30pm RISC-V Member Company Introductions Various RISC-V Foundation Member Companies
2:15pm RISC-V Foundation Mini Trade Show Various RISC-V Foundation Member Companies
5:00pm Adjourn for the Day

Tuesday, May 9th, 2017 6th RISC-V Workshop Day 1

Time Event Speaker, Affiliation Media
8:00am Registration and Networking Breakfast
8:45am 6th RISC-V Workshop Introduction Rick O’Connor, RISC-V Foundation
9:00am Taking RISC-V to Mainstream ASICs Charlie Su, Andes Technology
9:30am Labeled RISC-V: A New Perspective on Software-Defined Architecture Zihao Yu, ICT Chinese Academy of Sciences
10:00am RISC-V Privileged Architecture Andrew Waterman, SiFive
10:30am Networking Break
11:00am RISC-V Foundation Update Rick O’Connor, RISC-V Foundation
11:15am RISC-V Technical Committee Update Yunsup Lee, SiFive
11:30am RISC-V Marketing Committee Update Arun Thomas, BAE Systems
11:45am Panel Discussion: RISC-V in China
12:30pm Networking Lunch
1:45pm Keynote Address: RISC-V at NVIDIA Frans Sijstermans, NVIDIA
2:30pm SCR1 – open-source RISC-V compatible MCU core with support Ekaterina Berezina, Syntacore
2:45pm Making RISC-V IP easy to play with and evaluate Jack Kang, SiFive
3:00pm Automated RISC-V Verification Flow Utilizing Simulation, Formal, and Emulation Technologies Marcela Zachariasova, Codasip
3:30pm Networking Break
4:00pm Reprogrammable Logic in a RISC-V based SoC Alok Sanghavi, Achronix
4:15pm Video/Imaging solution on Microsemi Devices using RISC-V Badal Nilawar, Microsemi
4:30pm A RISC-V Instruction-set extension for baseband processing applications Cecil Accetti, Shanghai Jiao Tong University
4:45pm Poster / Demo Previews ~ 2min per presenter
5:15pm Transition to Reception
5:30pm Networking Reception, Posters Sessions and Demos
9:00pm Adjourn for the Day

Wednesday, May 10th, 2017 6th RISC-V Workshop Day 2

Time Event Speaker, Affiliation Media
8:00am Networking Breakfast
9:00am PULP an open source initiative building on top of RISC-V Eric Flamanad, ETH-Zurich
9:30am The 4th lowRISC release: Tagged memory and minion cores Wei Song, University of Cambridge / lowRISC
10:00am Status of the RISC-V Memory Consistency Model Daniel Lustig, NVIDIA
10:30am Networking Break
11:00am Keynote Address: Impedance Matching Expectations Between RISC-V and the Open Hardware Community Bunnie Huang
12:00pm Networking Lunch
1:30pm Panel Discussion: RISC-V Ask Me Anything
2:15pm Modern Software Development Methodology for RISC-V Devices Larry Lapides, Imperas
2:45pm RISC-V Debug Updates Megan Wachs, SiFive
3:15pm Networking Break
3:45pm RISC-V Hardware Accelerated Dynamic Binary Translation Simon Rokicki, IRISA
4:15pm Dual-core Lockstep Processor using RISC-V Softcores Sathish Odiga, Microsemi
4:30pm 28 Microwatt RV32IMAC Lauri Koskinen, Minima Processor
4:45pm 6th RISC-V Workshop Conclusion Rick O’Connor, RISC-V Foundation
5:00pm End of Workshop

Thursday, May 11th, 2017 RISC-V Foundation Member Meetings

(detailed agenda to be announced)