7th RISC-V Workshop Showcases Breadth of the RISC-V Ecosystem with More Than 45 Sessions Featuring Technology Leaders

Attendees will learn about notable RISC-V updates, projects and implementations across the globe

WHAT: 7th RISC-V Workshop

WHERE: Western Digital, 951 Sandisk Dr., Milpitas, Calif. 95035, Building 2

WHEN: Tuesday, Nov. 28 to Thursday, Nov. 30, 2017

DETAILS: The RISC-V Foundation is hosting the 7th RISC-V Workshop, bringing its expansive, international ecosystem together to discuss current and prospective RISC-V projects and implementations, as well as collectively drive the future evolution of the instruction set architecture (ISA) forward. Born in academia and research, the RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

The 7th Workshop will feature more than 45 sessions from leading technology companies and research institutions discussing the RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and much more. Keynote sessions will include Martin Fink, executive vice president and chief technology officer of Western Digital, and Linton Salmon, program manager at DARPA. The event schedule is as follows:

  • Tuesday, Nov. 28 and Wednesday, Nov. 29, 2017 – The first two days of the event will highlight RISC-V updates, projects and implementations. On Nov. 28 at 6 p.m. PT there will be a networking reception with poster sessions and demos.
  • Thursday, Nov. 30, 2017 – The last day of the Workshop will be limited to members of the RISC-V Foundation and will consist of Technical and Marketing Committee meetings to progress the work currently underway within the various RISC-V Task Groups.

To view the full agenda and register for the event, please visit: https://riscv.org/2017/10/7th-risc-v-workshop-agenda/

For press interested in attending, please email: risc-v@racepointglobal.com to receive your complimentary pass.

                                                                                                                                                             

About RISC-V Foundation

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 100 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.

 

Media Contacts:

Allison DeLeo

Racepoint Global for RISC-V Foundation

Phone: +1 (415) 694-6700

risc-v@racepointglobal.com

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