RISC-V E-Newsletter October 2017

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As we are gearing up for the 7th RISC-V Workshop, hosted by Western Digital in Milpitas, Calif. from Nov. 28 to Nov. 30, 2017, we have been thrilled to see the influx of submissions for talks and poster presentations. We are excited to unveil the full agenda which you can view here. The first two days of the event are packed with compelling presentations on RISC-V projects underway and keynotes from technology leaders Martin Fink, CTO at Western Digital, and Linton Salmon, program manager at DARPA. On Tuesday evening we will have a networking reception with poster sessions and demos. The third day of the event will feature RISC-V Foundation Technical and Marketing Committee meetings, limited to members of the RISC-V Foundation.

RISC-V has also been well-represented at recent industry conferences including Hot Chips 29, ORConf 2017 and The Linley Processor Conference. At Hot Chips, SiFive hosted a session on its RISC-V SoC and representatives from several major universities discussed Celerity, an open source RISC-V SoC with a neural network accelerator fabric. At ORConf 2017, attendees received updates on RISC-V projects in motion including the lowRISC platform, the PULP platform and Clifford Wolf’s formal verification tool. Ahead of the Linley Processor Conference, the RISC-V Foundation hosted a dinner with influential media and analysts to provide them with an update on the Foundation’s momentum and updates from several member companies. At the event, RISC-V exhibited new implementations with members including Codasip, Dover Microsystems, Microsemi and SiFive. Additionally, SiFive gave a talk about its new U54-MC RISC-V Core IP, and UltraSoC discussed fostering a system-level approach to SoC design.

We look forward to seeing everyone at the Workshop next month!

Israel Innovation Authority Creates RISC-V Group

The Israel Innovation Authority kicked off a new working group called GenPro to develop a rapid, efficient and independent processing platform based on RISC-V. The working group, comprised of academic researchers and industry organizations, plans to develop software and hardware technology beneficial for the individual companies while also efficiently using resources to create advanced software and hardware.

1680 Core RISC-V Design at Hot Chips

Jan Gray at Gray Research LLC presented a poster on GRVI Phalanx, a parallel processor overlay framework designed to simplify accelerator development. The poster highlighted a 1680 core design with 26 MB of SRAM on an XCVU9P FPGA, the first operational kilocore RISC-V, the first kilocore 32b RISC in an FPGA and the most 32b RISC cores on a chip in any technology. The poster also showcased plans and ideas for programming models and tools, in addition to recent work towards AWS F1 and PYNQ-Z1 general availability.

Welcome to our newest members!

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News

Microsemi Launches Mi-V Ecosystem to Accelerate Adoption of RISC-V

Dover Microsystems Launches CoreGuard

SiFive Launches First RISC-V Based CPU Core with Linux Support

SEGGER Adds Support for SiFive’s Coreplex IP to its J-Link Debug Probe

SiFive and UltraSoC Partner to Accelerate RISC-V Development Through DesignShare

SiFive and Rambus to Provide IP to the ‘DesignShare’ Economy

Codasip Announces Latest RISC-V Processor

Bill Wong at Electronic Design Reviewed SiFive’s HiFive1 RISC-V Board

Chantelle Dubois at All About Circuits Writes About How RISC-V Continues to Expand

Events

First Workshop on Computer Architecture Research with RISC-V (CARRV 2017), Boston, MA, Oct. 14, 2017, co-located with MICRO 2017.

International System-on-Chip (SoC) Conference at the University of California, Irvine from Oct. 18 – 19, 2017.

BSDTW 2017 at the Beitou Resort in Taipei City, Taiwan from Nov. 11-12, 2017.

Register for the 7th RISC-V Workshop hosted by Western Digital in Milpitas, Calif. on Nov. 28-30, 2017.

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