RISC-V Ecosystem to Present at 15th International System-on-Chip (SoC) Conference, Exhibit & Workshops

Six Companies from the RISC-V Ecosystem to Host Speaking Sessions at Conference

WHERE:

The 15th International System-on-Chip (SoC) Conference, Exhibit & Workshops, University of California, Irvine (UCI) , Irvine, Calif., 92697, Calit2 Building 2

WHEN:

Wednesday, Oct. 18 to Thursday, Oct. 19, 2017

WHAT:

The RISC-V Foundation will feature six member organizations at this year’s International SoC Conference. Ted Speers, VP and Head of Product Architecture and Planning for Microsemi SoC Group, a founding RISC-V member, is a keynote speaker addressing the challenges and possibilities of the open, free RISC-V ISA. Additionally, Foundation members including Codasip, Dover Microsystems, Imperas, SiFive and UltraSoC will present at this year’s show. RISC-V speaking sessions include:

  • Keynote: “RISC-V Challenges and Possibilities
    • When: Wednesday, Oct. 18, 2017 at 1 – 1:50 p.m. PT
    • Who: Ted Speers at Microsemi
  • Introducing the New RISC-V U54 Coreplex
    • When: Wednesday, Oct. 18, 2017 at 1:50 – 2:20 p.m. PT
    • Who: Jack Kang at SiFive
  • RISC-V Models and Simulation Enable Early Software Bring Up
    • When: Wednesday, Oct. 18, 2017 at 2:20 – 2:50 p.m. PT
    • Who: Larry Lapides at Imperas Software Ltd.
  • System-wide Visibility and Analytics
    • When: Wednesday, Oct. 18, 2017 at 2:50 – 3:20 p.m. PT
    • Who: Gajinder Panesar at UltraSoC
  • The Dover PIPE: Processor Interlocks for Policy Enforcement
    • When: Wednesday, Oct. 18, 2017 at 3:30 – 4 p.m. PT
    • Who: Steven Milburn at Dover Microsystems 
  • A High-Level Design Methodology for RISC-V Processor Development
    • When: Wednesday, Oct. 18, 2017 at 4 – 4:30 p.m. PT
    • Who: Dan Ganousis at Codasip
  • RISC-V and prpl: Why RISC-V will Become the Most Secure Processor Architecture
    • When: Thursday, Oct. 19, 2017 at 4 – 4:30 p.m. PT
    • Who: Art Swift at prpl Foundation

To schedule a meeting with RISC-V or a member organization please email: risc-v@racepointglobal.com. To learn more about the RISC-V Foundation, its open, free architecture and membership information, please visit: https://riscv.org.                                                                                                                                              

About RISC-V Foundation

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 70 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.

Media Contacts:

Allison DeLeo
Racepoint Global for RISC-V Foundation
Phone: +1 (415) 694-6700
risc-v@racepointglobal.com

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