RISC-V At Embedded World 2018

Join us at the Embedded World 2018 Exhibition & Conference in Nuremberg, Germany from Feb. 27 to March 1, 2018 at the NürnbergMesse.

Visit Our Booth Featuring Six Member Companies

The RISC-V Foundation booth will feature pods from member companies Antmicro, GreenWaves Technologies, Imperas, SyntacoreUltraSoC and VectorBlox. Visit us in Hall 3A, booth 3A-419.
           
           
           

Check Out Our Members’ Booths

Additional RISC-V member companies will be located at the following booths:

Take Part In Our Scavenger Hunt To Win Prizes

We’ll also be hosting a fun scavenger hunt! You can find the scavenger hunt form at the RISC-V Foundation booth (Hall 3A, booth 3A-419). To participate, you will need to visit the booths of each of our additional participating member companies: Antmicro, Ashling Microsystems, Cortus, Express Logic, Lauterbach, Microsemi, SEGGER Microcontroller, Trinamic and Western Digital.

At each booth, please speak with a company representative to receive a RISC-V sticker. Return your completed form to the RISC-V Foundation booth and share your business card to be entered to win one of the grand prizes.

Attend The RISC-V Talk Track

Embedded World invited the Foundation to host a full-day RISC-V track on Tuesday, Feb. 27. The speaking track, called RISC-V Class, will feature 10 half hour presentations from member companies, universities and the Foundation. During the RISC-V track, speakers will discuss the role of the RISC-V ecosystem in advancing innovation and growth in the semiconductor and embedded systems industries. 

Read About Each RISC-V Session

  • Running RTOS on RISC-V
    • When: 9:30 a.m. – 10 a.m. CET
    • Who: Tim Morin, Microsemi Corporation

    In this presentation we will demonstrate both open source and commercial RTOS available for RISC-V. The attendees will be guided through the components of the Mi-V RISC-V ecosystem, how to bring up an RTOS, shown example projects and how to get started. Open source RTOS such as FreeRTOS, LiteOS as well as commercial vendors Micrium’s uC OSII and Express Logic ThreadX will be walked through so attendees can just start their own design.

  • RISC-V: Emulation and Rich, Non-Intrusive Analytics Address Verification Complexity
    • When: 10 a.m. – 10:30 a.m. CET
    • Who: Rupert Baines, UltraSoC and and Russ Klein, Mentor Graphics

    One of the biggest challenges in SoC design is systemic complexity. Verification means we can be confident in the test coverage of individual blocks, but when these are integrated into a whole system the complexity increases and problems slip through.

    This is especially the case for heterogeneous, multi-core systems or those with lots of different IP blocks. In this class of system, the interactions between hardware and software, software / software or between the many different elements can cause issues. Indeed, many of today’s chips are so complex it is impossible for the design team who creates them to fully understand their operation in-life or in field. Typically those issues cannot be found in simulation and verification because of the time involved (subtle issues that occur on a time scale of days).

    By monitoring actual traffic in silicon at wire-speed, UltraSoC helps identify system-level problems.

    Because it integrates local intelligence for filtering and statistics, the amount of information extracted is low compared to the raw data passing through. This makes it easier to find even subtle issues. UltraSoC hard wires non-intrusive, vendor neutral ‘smart’ analytics circuitry into the chip to give full visibility making it easy to understand everything in a chip.

    The Mentor Veloce emulation platform enables high-speed emulation of complex SoCs to quickly identify design issues under critical traffic conditions and enable users to improve device performance and reduce time to market.

    The integration of UltraSoC technology at the chip level extends the use of the Veloce platform to prototyping, enabling real word actual traffic to be gathered and analyzed. That includes visualizations, statistics and comparing modelled / predicted behavior with actual / captured behavior to identify discrepancies.
    Those discrepancies might be bugs (e.g. deadlock), or could equally be inefficiencies.

    By reviewing the actual bus traffic from UltraSoC, engineers can identify aspects such as contention, underutilization and opportunities to improve performance and reduce power dissipation. This builds on the power and flexibility of the Mentor Veloce emulation platform.

    Crucially, these issues will be those that were not observed (indeed, in many cases could not be observed) in the slow virtual world of traditional simulation, but with this combination can easily be observed and addressed. This approach also enables an easy transition from emulation to post-silicon implementation, giving a seamless flow from virtual to physical, and to in-life / in-field deployment and optimization. UltraSoC IP includes protocol-aware bus monitors for all major interconnects and buses, including CHI, AXI, OCP, AHB, etc. making this solution very versatile. It also supports processors (ARM, MIPS, CEVA, XTensa, RISC V etc.), co processors and custom logic (with sophisticated logic analyzer functionality) into one integrated development view.

  • Cycle Approximate Timing Simulation of RISC-V Processors
    • When: 10:30 a.m. – 11 a.m. CET
    • Who: Lee Moore, Imperas

    For RISC-V semiconductor vendors to win embedded system sockets, their customers are going to want to know about the timing and power consumption of those SoCs.

    Historically, architectural estimation, analysis and optimization has been done using either manual spreadsheets, hardware emulators, FPGA prototypes, cycle approximate simulators or cycle accurate simulators. These all have significant drawbacks: insufficient accuracy, high cost, RTL availability (meaning that the technique is only available later in the project when the RTL design is complete), low performance.

    Instruction accurate software simulation, or virtual platforms, have the speed necessary to cover the range of system scenarios, can be available much earlier in the project, and are typically 5x less expensive than cycle approximate or cycle accurate simulators.

    Previously, because of a lack of timing information in the models and simulator, virtual platforms could not be used for timing estimation. We report here on a technique for dynamically annotating timing information to the software simulation results. This has achieved accuracy of better than +/-15%, which is normally good enough for most architectural exploration and system analysis.

    In the Open Virtual Platforms (OVP) processor model architecture it is possible to create a standalone library module with entry points that are called when instructions are executed. This library can introspect the running system and calculate an estimate for the cycles taken to execute the current instruction. Not only can these add-on libraries dynamically inspect the running system estimate timing affects, they can annotate calculated instruction cycle timing back into the simulation and affect timing of the simulation.

  • Securing RISC-V Machines Dynamically with Hardware-Enforced Metadata Policies
    • When: 11:30 a.m. – Noon CET
    • Who: Steven Milburn, Dover Microsystems

    Dover Microsystems’ IP implements a security solution for RISC-V machines which is more robust, flexible, and updatable than anything available today in competitor processor architectures. We do this with a hybrid hardware-software implementation of metadata policy enforcement, where we check the validity of every instruction executed against a set of software-defined metadata policies, and queue writes to memory or peripherals until validation is complete. We will demonstrate how we apply our metadata policy concepts in hardware, software, and the toolchain to implement policies for Data Confidentiality and Compartmentalization. Dover Microsystems will have a live demonstration running on an FPGA with a RISC-V core, and will present the power, performance, area, and security (PPAS) impacts on that system.

  • RISC-V ISA and Foundation Overview
    • When: Noon – 12:30 p.m. CET
    • Who: Rick O’Connor, RISC-V Foundation

    The free and open RISC-V (“risk-five”) Instruction Set Architecture (ISA) began development at UC Berkeley in 2010, with the frozen base user ISA specification released in May 2014, and has since seen rapid uptake around the globe, including the first commercial shipments. The RISC-V effort distills over 30 years of processor research at UC Berkeley and elsewhere into an extensible instruction set that can be fully customized.

    This talk will cover features of the RISC-V ISA design, which has the goals of scaling from deeply embedded implementations for IoT up to the largest warehouse-scale computers, with support for extensive customization. We’ll also detail the uptake of RISC-V globally and the development of the RISC-V ecosystem, including Western Digital’s “billion RISC-V core commitment” and provide a RISC-V Foundation update.

  • A RISC V-Based Open Hardware Platform for Wearable
    • When: 2:30 p.m. – 3 p.m. CET
    • Who: Stefan Mach, ETH Zurich

    Wearable smart sensing is a promising technology to enhance user experience in sport/fitness, as well as health and human monitoring. Wearable sensing systems, as also Internet of Thing (IoT) systems, not only provide continuous data monitoring and acquisition, but are also expected to process, and make sense of the acquired data by classification in similar ways as human experts do. Supporting continuous “smart” operation on ultra-small batteries poses unique challenges in energy efficiency.

    In this work, we present an ultra-low-power open embedded platform that hosts a scalable array of analogue-to-digital converters for biomedical and inertial sensors, and it can process data on-board with machine learning algorithms (i.e. SVM, KNN, Neural Networks) in an energy efficient manner. The platform’s compute engine is a heterogeneous multi-core parallel ultra-low power (PULP) processor based on RISC-V, capable to deliver up to 1.8 GOPS and embedding hardware accelerators. These features are provided with 10 mW power consumption (168 MHz, 0.78V Core voltage), which makes the platform ideal for battery-powered activities typically of wearable applications, with a 30x energy efficiency increase compared to standard microcontrollers (MCUs) with similar power budgets.

    The wearable platform can be interfaced with “electronic skin” (E-skin) arrays of tactile sensors with up to 64 channels, and ECG/EMG sensors up to 8 channels. Moreover, the platform provides a Bluetooth Low Energy 5.0 module for energyefficient wireless connectivity.

  • A RISC-V Based Heterogeneous Cluster
    • When: 3 p.m. – 3:30 p.m. CET
    • Who: Davide Rossi, University of Bologna

    IoT end-nodes require high performance and extreme energy efficiency to cope with complex and near-sensor data analytics algorithms. Processing on multiple programmable processors operating in near-threshold is emerging as a promising solution to exploit the energy boost given by low-voltage operation, while recovering the related frequency degradation with parallelism.

    In this abstract, we present a heterogeneous computing architecture where a parallel ultra-low-power (PULP) cluster of RISC-V processor is extended with a reconfigurable Integrated Programmable Array (IPA) accelerator. The cluster architecture is built around 8 32-bit RISC-V cores based on a four pipeline stages micro-architecture optimized for energy-efficient operation, sharing a 64KB multi-banked L1 scratchpad memory for efficient parallel processing. The ISA of the processors is extended with instructions targeting energy efficient digital signal processing such as hardware loops, load/store with pre/post increment, vectorial operations, and instructions targeting energy efficient fixed-point arithmetic operations. While programmable processors guarantee programming legacy to manage peripherals, as well as the global program flow and high performance in execution of data-parallel compute intensive kernels, significant performance and energy efficiency boost can be achieved offloading control-intensive kernels to the IPA.

    The IPA is composed of an array of simple processing elements featuring a 20-instructions ISA connected through a 2-dimensional tours. From a micro-architectural viewpoint, point-to-point data communication between simple processing elements (PEs) represents the key advantage of the IPA over energy-hungry data sharing over the L1 memory that is required when using a homogeneous processor cluster architecture for parallel processing. Reducing the pressure on the L1 memory, and exploiting instruction-level parallelism on top of data level-parallelism of multiple instruction processors, the proposed heterogeneous cluster outperforms an 8-core homogeneous architecture by up to 4.8x in performance and 4.5x in energy efficiency when executing a mix of control-intensive and data-intensive kernels typical of near-sensor data analytics applications.

  • Precisely Engineered RISC-V Embedded Processors in 30 Days
    • When: 4 p.m. – 4:30 p.m. CET
    • Who: Keith Graham, University of Colorado Boulder

    IoT end-nodes require high performance and extreme energy efficiency to cope with complex and near-sensor data analytics algorithms. Processing on multiple programmable processors operating in near-threshold is emerging as a promising solution to exploit the energy boost given by low-voltage operation, while recovering the related frequency degradation with parallelism.

    In this abstract, we present a heterogeneous computing architecture where a parallel ultra-low-power (PULP) cluster of RISC-V processor is extended with a reconfigurable Integrated Programmable Array (IPA) accelerator. The cluster architecture is built around 8 32-bit RISC-V cores based on a four pipeline stages micro-architecture optimized for energy-efficient operation, sharing a 64KB multi-banked L1 scratchpad memory for efficient parallel processing. The ISA of the processors is extended with instructions targeting energy efficient digital signal processing such as hardware loops, load/store with pre/post increment, vectorial operations, and instructions targeting energy efficient fixed-point arithmetic operations. While programmable processors guarantee programming legacy to manage peripherals, as well as the global program flow and high performance in execution of data-parallel compute intensive kernels, significant performance and energy efficiency boost can be achieved offloading control-intensive kernels to the IPA.

    The IPA is composed of an array of simple processing elements featuring a 20-instructions ISA connected through a 2-dimensional tours. From a micro-architectural viewpoint, point-to-point data communication between simple processing elements (PEs) represents the key advantage of the IPA over energy-hungry data sharing over the L1 memory that is required when using a homogeneous processor cluster architecture for parallel processing. Reducing the pressure on the L1 memory, and exploiting instruction-level parallelism on top of data level-parallelism of multiple instruction processors, the proposed heterogeneous cluster outperforms an 8-core homogeneous architecture by up to 4.8x in performance and 4.5x in energy efficiency when executing a mix of control-intensive and data-intensive kernels typical of near-sensor data analytics applications.

  • RISC-V in High Computing, Ultra-Low-Power, Programmable Circuits
    • When: 4:30 p.m. – 5 p.m. CET
    • Who: Eric Flamand, GreenWaves Technologies

    Today’s ultra-low power edge devices that need to operate for a long period of time on a battery are limited to relatively data poor sensors such as temperature, pressure, motion. For the next generation enabling data rich sensors for these edge devices opens great opportunities but also poses some serious challenges.

    1) How does one transform a large amount of input data into something that is several orders of magnitude smaller?

    2) Much more input data implies much more processing capabilities. How does one offer multi-giga operations per second while keeping a power consumption in the mW range?

    3) Edge devices tend to have irregular activity patterns. How does one remain energy efficient in a range of workload that goes from 0 to multi GOPs?

    4) Finally, and just as importantly, how to do all of this while retaining a simple programming model in a context where, for the sake of energy efficiency, hardware complexity must be kept minimal?

    In this paper we will show how a combination of architectural innovation, design trade-offs and tools innovation that makes it possible to tackle these challenges. We will show how the RISC-V’s extendable ISA allows specific optimizations for energy efficiency and enables architectural innovation.

    We will use several real-life examples from the image and audio domain to illustrate how an actual multi core RISC-V processor implementation can perform on these applications and what the path is to efficient implementation.
    The focus will be a step by step analysis of how hardware resources are used (vectors, parallelization, synchronization, power management, memory management).

  • Efficiency of the RISC-V ISA-Level Custom Extension
    • When: 5 p.m. – 5:30 p.m. CET
    • Who: Grigory Okhotnikov, Syntacore

    Recent slowdowns in the semiconductor technology scaling and “traditional” CPU performance growth established platform heterogeneity and HW specialization as a fundamental trend in the computer architecture and design. Contemporary SoCs are increasingly heterogeneous, but dominating use case is addition of the workload-specific accelerators and driver model for SW deployment, which limits resources reuse and efficiency of the resulting solution.

    The open RISC-V ISA standard includes support for user-defined extensions. Although technologies, based on the ISA extensibility are well known and have been both extensively explored in the academia and successfully applied in the industry in several cases, RISC-V for the first time enables such technologies in the main system sockets for a wide range of applications.
    In this paper, authors explore efficiency of the ISA-level RISC-V extensibility for acceleration of the familiar AES algorithms suite. We study ISA suitability and limitations for such acceleration and measure performance and efficiency of a developed custom extension. Newly introduced ISA primitives include support for the regular and last round encryption and decryption as well as keygen assist and operate over the standard RV32GC register files. Implementation is practical and includes support for all the variations of the algorithm defined by the AES standard.

    All the extensions have been prototyped in HW. The demonstrated results are based on the real-time FPGA implementation and end-to-end benchmarking using accelerated OpenSSL library with extensions support. The prototype setup includes RISC-V RV32GC based processor core with GCC toolchain, modified to support the designed custom extension. The resulting implementation demonstrates more than 50x ciphers speed-ups vs base, SW-only implementation for the RISC-V RV32GC system at the expense of a very modest additional HW footprint (~2k Gates). Measured performance is compared with HW-accelerated results from the contemporary commercial CPUs, currently available on the market, and proves to be competitive.

Other Presentations

Stop by the Microsemi booth (Hall 1 / 1-431) to attend additional presentations about RISC-V. RISC-V Foundation Executive Director Rick O’Connor will be leading sessions discussing the RISC-V ISA and ecosystem. Microsemi will be leading talks about Microsemi’s Mi-V RISC-V ecosystem. For more session details, please visit: https://www.microsemi.com/details/326-embedded-world-2018.

Learn More

You can check out the full Embedded World program here. To schedule a meeting with RISC-V or a member organization, please email: ew2018@riscv.org.

To learn more about the RISC-V Foundation, its open, free architecture and membership information, please visit: https://riscv.org. Stay up-to-date about the latest RISC-V news by following us on Twitter and LinkedIn.

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