RISC-V E-Newsletter Winter 2018

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Ecosystem Momentum

Last year was a hallmark one for the RISC-V Foundation. Our membership continued to grow at a rapid pace, surpassing 100 organizations, individuals, academics and universities. We put on the biggest RISC-V Workshop yet with 500+ attendees, and witnessed the industry buzzing about the exciting member news from the show. RISC-V members and enthusiasts gave talks about RISC-V at conferences and events around the world, including Hot Chips 29, the International SoC Conference, the Linley Processor Conference, ORConf 2017 and RISC-V Day 2017 Tokyo.

Continuing the momentum, the Foundation and our members will be giving RISC-V talks at upcoming shows including Embedded World 2018 in Germany, the IEEE International Symposium on HPC in Austria and DAC 2018 in San Francisco. We also look forward to the next event hosted by the Foundation, the 8th RISC-V Workshop in Barcelona. Stay tuned for more details about the event, taking place May 7 to 10 at BarcelonaTech (UPC).

Thank you for your continued support of the RISC-V Foundation and its ecosystem. We look forward to a fantastic year ahead in 2018 and beyond.

Events

HPCA 2018: 24th IEEE International Symposium on HPCA at Austria Trend Eventhotel Pyramide in Vienna, Austria from Feb. 24 – 28, 2018.

Embedded World 2018 Exhibition & Conference at NürnbergMesse in Nuremberg, Germany from Feb. 27 – March 1, 2018. For more information about our activities at Embedded World 2018, please visit here.

8th RISC-V Workshop at BarcelonaTech (UPC) in Barcelona from May 7 – 10, 2018.

Design Automation Conference (DAC) at Moscone Center West in San Francisco, Calif. from June 24 – 28, 2018.

Ecosystem News

February 2018:
Hackaday: A RISC-V That The Rest Of Us Can Understand
insideHPC: Realizing Exabyte-Scale PM Centric Architectures And Memory Fabrics
Microsemi: SiFive Joins Microsemi’s New Mi-V Ecosystem To Accelerate Adoption Of RISC-V Open Instruction Set Architecture
SiFive: SiFive Appoints CFO to Executive Team
TechRepublic: Hi-Five Unleashed: The First Linux-Capable RISC-V Single Board Computer Is Here

January 2018:
Barron’s: Western Dig, Nvidia On Board with ‘RISC-V,’ So Pay Attention, Says Benchmark
eeNews Europe: Codasip’s Studio: 7th Edition For The Easy Configuration Of RISC-V Processors
eeNews Europe: Dresden Firm Takes FDSOI Down To 0.4V
EE Journal: The Bisquick Alternative: SiFive Uses RISC-V To Simplify SoC Creation
Electronic Design: 11 Myths About the RISC-V ISA
Electronic Design: These 2017 Embedded Trends Will Thrive In 2018
WikiChip Fuse: Esperanto Exits Stealth Mode, Aims At AI With A 4,096-core 7nm RISC-V Monster
New Electronics: Avalanche Board Featuring Microsemi’s PolarFire FPGAs
RISC-V Foundation: Building A More Secure World With The RISC-V ISA
Semiconductor Engineering: Predictions: Manufacturing, Devices And Companies
Semiconductor Engineering: Reflection On 2017: Design And EDA
Sensors Online: RISC-V Processor Trace IP An Industry First
SiFive: A Look Back: 7th RISC-V Workshop
SiFive: SiFive Welcomes Former Intel Corporate VP to Executive Team

December 2017:
AB Open: CRU: PULP Interview, HiFive Unleashed, 3D Printed Sensors, And More
AnandTech: Western Digital to Use RISC-V for Controllers, Processors, Purpose-Built Platforms
Design And Reuse: Reduced Energy Microsystems Joins FDXcelerator Program To Bring RISC-V IP To
Embedded Computing Design: Five Minutes With…Jack Kang, VP Of Product And Business Development, SiFive
Embedded Computing Design: Five Minutes With…Rick O’Connor, Executive Director, RISC-V Foundation
Embedded Computing Design: Inflection Point For RISC-V: The 7th RISC-V Workshop In Silicon Valley
eeNews Europe: Extendable Platform Kit to Ease Adoption Of FPGA-Based RISC-V Designs
EE Times: 8 Top Innovations Of 2017
EE Times Japan: Article On RISC-V Day 2017 Tokyo
EE Journal: Visualizing Real-Time Issues: Swedish Company Gives Developers Better Insight
Electronic Design: Getting “Creative” With RISC-V
Electronic Design: Leveraging RISC-V For AI And Machine Learning
Microsemi: SiFive Joins Microsemi’s New Mi-V Ecosystem
SEGGER: SEGGER Presents RTOS, Stacks, Middleware For RISC-V
Semiconductor Engineering: Reflections On 2017: Manufacturing and Markets
SiFive: RISC-V QEMU Part 1: Privileged ISA v1.10, HiFive1 And VirtIO

Welcome to our newest members!

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