RISC-V Ecosystem Highlights Momentum Across Asia At RISC-V Day In Shanghai

RISC-V members to present on RISC-V based products and solutions

WHERE: Fudan University, Handan Campus, 220 Handan Rd, WuJiaoChang, Yangpu Qu, Shanghai Shi, China, 200433

WHEN:  Saturday, June 30, 2018, 8 a.m. – 6 p.m. CST

WHAT:  The RISC-V Foundation will share updates on new projects and implementations from its international membership at the RISC-V Day in Shanghai, with a focus on the growth of the RISC-V ecosystem across Asia. RISC-V Foundation member companies Andes Technologies, Codasip, GreenWaves Technologies, ICT, Microsemi, SiFive and Syntacore will present at RISC-V Day in Shanghai. Speaking sessions include:

  • Comprehensive RISC-V Solutions for AIoT
    • When: 9 a.m. – 9:30 a.m. CST
    • Who: Charlie Su, Andes Technology
  • The SCR Family of RISC-V Compatible Processor IP
    • When: 9:30 a.m. – 10 a.m. CST
    • Who: Pavel Khabarov, Syntacore
  • Introducing the New IP Series
    • When: 10 a.m. – 10:30 a.m. CST
    • Who: Jack Kang, SiFive
  • Ultra-Low-Power Open-Source Core to Boost the Spread of RISC-V in China
    • When: 11 a.m. – 11:30 a.m. CST
    • Who: Bob Hu, Open Source HummingBird E203 RISC-V Processor Core Group
  • Enhancements to Tools for Automated Generation of RISC-V Processors
    • When: 11:30 a.m. – 11:45 a.m. CST
    • Who: Zdenek Prikryl, Codasip
  • Using RISC-V in High Computing, Ultra-Low Power, Programmable Circuits for Inference on Battery Operated Edge
    • When: 1:30 p.m. – 2 p.m. CST
    • Who: Martin Croome, GreenWaves Technologies
  • OpenPrefetch: Let There Be Industry-Competitive Prefetching in RISC-V Processors Open-Prefetch
    • When: 2 p.m. – 2:15 p.m. CST
    • Who: Bowen Huang and Yungang Bao, ICT
  • Ways to Reduce RISC-V Soft Processor Footprint
    • When: 2:15 p.m. – 2:30 p.m. CST
    • Who: Ruigang Wan, Chengdu University
  • Firmware Freedom: Coreboot for RISC-V
    • When: 2:30 p.m. – 3 p.m. CST
    • Who: Xiang Wang, TYA and Shawn Chang, HardenedLinux
  • Defeating the Recent AnC Attack in RISC-V SoC
    • When: 3 p.m. – 3:15 p.m. CST
    • Who: Rui Hou and Xiaoxin Li, Institute of Information Engineering, Chinese Academy of Sciences
  • Fedora on RISC-V – Status Update
    • When: 3:45 p.m. – 4:15 p.m. CST
    • Who: Wei Fu, Red Hat
  • SylixOS (SMP RTOS) Running on RISC-V
    • When: 4:15 p.m. – 4:45 p.m. CST
    • Who: JinXing Jiao, ACOINFO
  • RT-Thread / RISC-V RT-Thread
    • When: 4:45 p.m. – 5 p.m. CST
    • Who: Yongxiang Liang and Bernard Xiong, RT Thread
  • Deep Learning Showcased on RISC-V With Linux using the Mi-V Unleashed Kit
    • When: 5 p.m. – 5:30 p.m. CST
    • Who: Krishnakumar R., Microsemi
  • Per-V Creative Board Designed for the RISC-V Community With Future Ecosystem Support
    • When: 5:30 p.m. – 5:45 p.m. CST
    • Who: Hualong Zhao, Perfxlab Company

 

For more information about RISC-V Day in Shanghai, please visit: https://tmt.knect365.com/risc-v-day-shanghai/ and to book your ticket, please visit: https://tmt.knect365.com/risc-v-day-shanghai/purchase/select-package.

 

To schedule a meeting with RISC-V or a member organization, please email: risc-v@racepointglobal.com. To learn more about the RISC-V Foundation, its open, free architecture and membership information, please visit: https://riscv.org.

 

About RISC-V Foundation

RISC-V (pronounced “risk-five”) is free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 100 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.

 

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