The Indian Institute of Technology Madras is hosting RISC-V Workshop, a free and open Instruction Set Architecture (ISA) that enables a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA aims to deliver a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
…Speaking about the importance of this event, Workshop Vice-Chair Prof. Kamakoti Veezhinathan, Computer Science and Engineering Department, IIT Madras, said, “The National Microprocessor Development Program, funded by Ministry of Electronics and Information Technology, Government of India, aims to develop indigenous microprocessor for the country. The processor code being developed as part of this program is based on RISC-V ISA.”
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