Embecosm Blog Post: Supporting The RISC-V Vector Extension In GCC And LLVM

I recently attended the GNU Tools Cauldron in Manchester, where Roger Espasa from Esperanto Technologies and I ran a BoF session on GCC support for the RISC-V Vector (V) extension. This is an interesting topic, because the V extension has features that aren’t present in any other supported SIMD / Vector Architecture. This post is a short writeup of the current state of efforts towards supporting the extension in both GCC and LLVM, and some pointers to where things appear to be going.

The RISC-V Vector Extension has some interesting features. Some highlights are:

  • A hardware vector length that is not just unknown at compile-time, but can also vary on a frequent basis,
  • A vector register file that can be reconfigured for different data types / sizes, and
  • Optional support for different data shapes in vector registers – e.g. scalar, vector, matrix.

A video of one of Roger’s previous tutorials gives a nice introduction and overview of the architecture.

At present the V extension design is not yet finalized – there are still possibilities for changes to the encodings and some instructions. The current working version of the proposal is kept in  the RISC-V-spec Github repository.


To read more, please visit: https://www.embecosm.com/2018/09/09/supporting-the-risc-v-vector-extension-in-gcc-and-llvm/