ABOpen Article: Western Digital Unveils Open SweRV RISC-V Core

Western Digital has unveiled its first in-house RISC-V core, dubbed SweRV, and it has confirmed plans to release it under an open source license early next year.

Part of a company initiative, started in 2017, to switch from proprietary instruction set architectures (ISAs) to the open RISC-V ISA across its storage processing products, Western Digital’s SweRV marks the company’s first public announcement of an in-house processing core. Based on the 32-bit RISC-V variant and designed for manufacturing on a 28nm CMOS process node, the part is claimed to clock up to 1.8GHz and offer performance of 4.9 CoreMarks per megahertz (CoreMarks/MHz).

“As Big Data and Fast Data continues to proliferate, purpose-built technologies are essential for unlocking the true value of data across today’s wide-ranging data-centric applications,” says Western Digital chief technology officer Martin Fink. “Our SweRV Core and the new cache coherency fabric initiative demonstrate the significant possibilities that can be realised by bringing data closer to processing power. These planned contributions to the open-source community and continued commitment of the RISC-V initiative offer exciting potential to accelerate collaborative innovation and data-driven discoveries.”

 

To read more, please visit: https://abopen.com/news/western-digital-unveils-open-swerv-risc-v-core/.

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