RISC-V hasn’t been a huge topic for us at ExtremeTech, but the fully open-source CPU instruction set architecture (ISA) has been building momentum in the industry over the past few years as more companies have signed on to build RISC V-compatible processors. While it’s not the first open-source ISA, RISC-V is designed to be used in a wider range of devices than some of the previous work in this space. Now, Western Digital has announced that it intends to build its own RISC-V processor, in what could be a major breakthrough moment for the ISA as a whole.
RISC-V has been under development for years and is intended to be a practical ISA for CPU development rather than strictly an academic exercise. Wikipedia’s entry on the ISA is fairly good if you’re looking for an overview. According to Western Digital, it’s making an investment in its new CPU, SweRV, as part of its goal to ship one billion RISC-V cores in its various storage products per year. WD will build the SweRV core, an open standard initiative for cache coherent memory over a network, (OmniXtend) and an open source RISC-V instruction set simulator. The first two projects are intended to improve Western Digital’s own efforts in the storage market, while the third is useful to the RISC-V community more generally (in addition to WD itself, of course).
To read more, please visit: https://www.extremetech.com/computing/281891-western-digital-announces-plans-for-its-own-risc-v-processor.