At the RISC-V Summit, Western Digital (WD) announced three open-source innovations related to the RISC-V instruction set architecture (ISA): a new open source RISC-V CPU core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator.
WD announced that it has built its own RISC-V core, which it calls “SweRV,” and that it intends to open source it. The CPU core features a two-way superscalar design, 32-bit in-order architecture, and nine stage pipeline.
WD also announced the “OmniXtend,” which is a new open approach to providing cache coherent memory over an Ethernet fabric, according to the company. It’s a memory-centric system architecture that provides open standard interfaces for access and data sharing across different types of processors, including CPUs, GPUs, machine learning accelerators, FPGAs, and others. The OmniXtend solution also offers support for future advanced fabrics that connect compute, storage, memory, and I/O components.
Finally, the company announced its open source SweRV Instruction Set Simulator (ISS), a program that simulates the execution of instructions on the SweRV processor. WD itself used the ISS to validate the design of the SweRV core with more than 10 billion instructions executed. WD expects the SweRV core and its corresponding simulator will advance the adoption of the open source RISC-V ISA.
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