The integration of powerful processors into stepper motor controllers, BLDC motors, brushed DC motors and voice coil motors allows for more design freedom and motion capabilities required in the future.
With the Reduced Instruction Set Computer V, abbreviated RISC-V, the University of California at Berkeley has teamed up with industry partners to create an open instruction set architecture. The aim was to make processors and cores, based on the architecture, usable for as many applications as possible.
This open instruction set structure of the software, unlike most instruction set architectures, is not patented and may be freely used due to the BSD (Berkeley Software Distribution) license. The most important criterion for RISC-V was to have an architecture that can not change over the years. The current instruction set architecture is codified, which results in a runnability of programs developed today, even on future processor cores, if they are based on the same basic ISA and identical extensions.
To read more, please visit: https://www.elektronikpraxis.vogel.de/welterster-foc-motorcontroller-mit-risc-v-als-single-chip-loesung-a-790933/. Please note that the original article is in German.