Linux Insider Article: Introduction To RISC-V: Nikos Kosyfidis Introduces Us To The World Of New Open Processor Architecture

Nikos Kosyfidis spoke at the highly successful FOSSCOMM 2018 conference about RISC-V, the open and free architecture for simple and less power-efficient processors running from small computers to the cloud. We asked Nikos to answer a few questions in order to understand more about RISC-V and to spread awareness for the open architecture.

LI: Nikos, first tell us a few words about what RISC-V is.

NK: Each processor has a model of operation that includes various commands (the assembly), types of data (integer, decimal, doubles, vectors, etc.) to register the memory access model, the handling of interrupts (e.g. timers) and traps (e.g. how to report a segfault or a wrong command) and more. This operating model is called the Order Set Architecture (ISA). When we say that our system is x86, amd64, arm64, mips, powerpc, etc., we mean that the processor follows the corresponding mode of operation.

The RISC-V mode of operation is currently comes in the form of 32-bit and 64-bit processors that can be either special purpose, like Arduino style microcontrollers, or general-purpose such as the processors on our computers and smartphones.


To read more, please visit: Please note that the original article is in Greek.