RISC-V E-Newsletter Winter 2019

Click HERE to Join the RISC-V Foundation Mail Lists

Ecosystem Momentum

There’s no question the RISC-V ecosystem is growing at an exponential pace. We’ve welcomed 22 new members since the previous newsletter and now have more than 210 members around the world. The momentum of the RISC-V Foundation is also evident in the increasing number of global events. The most notable is our inaugural RISC-V Summit that took place in Santa Clara from Dec. 3-6, 2018 with over 1,100 registered attendees from more than 20 different countries. Over double the size of the 7th RISC-V Workshop in November 2017, the RISC-V Summit featured a multi-track conference, tutorials and exhibitions, as well as keynotes from Antmicro, Facebook, Microchip Technology, NXP, Qualcomm, SiFive, UC Berkeley and Western Digital. Slides and videos from the presentations are available on the proceedings page and a video with highlights from the RISC-V Summit can be found on the website here.

At the RISC-V Summit, the RISC-V Foundation awarded Daniel Lustig, Chair of the RISC-V Memory Model Task Group and renowned research scientist at NVIDIA Corporation, the inaugural 2018 RISC-V Foundation Board of Directors’ Award. This award recognized RISC-V community members for their dedicated leadership and continued technical contributions to advancing the RISC-V ISA.

Also at the RISC-V Summit, the RISC-V Foundation announced the winners of the RISC-V SoftCPU Contest. Thanks to support from our contest sponsors Antmicro, Google, Lattice Semiconductor and Microchip Technology, our first contest was a success. We look forward to more contests in the future.

This past October, the RISC-V ecosystem and surrounding community in Japan gathered for the RISC-V Day in Tokyo. We would like to thank Keio University for hosting the one-day RISC-V event. In November, the RISC-V Foundation and The Linux Foundation officially announced a joint collaboration agreement to enhance open source development and adoption of the RISC-V ISA. The Linux Foundation plans to provide various resources for the RISC-V ecosystem, including: training programs, infrastructure tools, as well as community outreach, marketing and legal expertise. Collaboration is already underway as The Linux Foundation and members of the RISC-V ecosystem are working on the “Getting Started” guides for running Zephyr, a small, scalable open source RTOS for connected, resource constrained devices, and Linux operating systems on RISC-V based platforms.

Interest in RISC-V Meetups has grown significantly in the U.S. and around the globe. Since our last newsletter, there were RISC-V Meetups in locations including Austinthe Bay AreaBristolCambridgeIsraelthe Rocky Mountain AreaVienna and Wroclaw for those interested in learning more about RISC-V.

In February, the RISC-V Foundation is exhibiting at Embedded World 2019 (Hall 3A, Booth 3A-536) with pods from member companies Andes Technology, CloudBEAR, GreenWaves Technologies, Imperas Software, SiFive, UltraSoC and Syntacore. Throughout the show the booth will feature talks from member companies, so we encourage everyone to stop by. We are also hosting a scavenger hunt, challenging visitors to visit different booths in the RISC-V ecosystem for the chance to win a prize. Don’t miss out on the variety of RISC-V talks in the Embedded World program; learn more here.

Mark your calendars for the RISC-V Workshop Taiwan from March 12-13 at the National Tsing Hua University and the RISC-V Workshop Zurich hosted by ETH Zurich from June 11-13. Tickets for the RISC-V Workshop Taiwan are available for purchase here. The deadline for the RISC-V Workshop Zurich Call for Speakers is Feb. 28; submit your proposal here.

Let us know where you would like to see an event next; we always appreciate your participation, feedback and involvement! Thank you for your continued support of the RISC-V Foundation and its growing ecosystem.

Upcoming Events

Design and Verification Conference and Exhibition (DVCON) at the Double Tree Hotel in San Jose, CA from Feb. 25-28, 2019. Don’t miss the panel on open ISAs, which will feature speakers from Andes Technology, Breker Verification Systems, Facebook, Imperas Software and XtremeEDA Corporation, and will be moderated by TIRIAS Research.

Pune RISC-V Meetup at Open Silicon Research in Pune, India on Feb. 2 at 10 a.m. IST.

RISC-V SweRV Core Deep Dive at Western Digital in Milpitas, Calif. on Feb. 21 at 5:30 p.m. PT.

Embedded World at NürnbergMesse in Nuremberg, Germany from Feb. 26-28, 2019.

RISC-V Workshop Taiwan at the National Tsing Hua University in Hsinchu, Taiwan from March 12-13, 2019.

RISC-V Workshop Zurich at ETH Zurich in Zurich, Switzerland from June 11-13, 2019.

Visit our events page to stay up-to-date with RISC-V events.

Ecosystem News

January 2019:
AB Open: Raspberry Pi Foundation Announces RISC-V Foundation Membership
AB Open: RISC-V Summit 2018 Highlight Video Celebrates A Banner Year
AdaCore: AdaCore Joins The RISC-V Foundation To Provide C And Ada Compilation Support
Andes Technology: Feature-Rich RISC-V IDE Available For Free Download
Bluespec: Bluespec Returns From Landmark RISC-V Summit; CTO Nikhil Leads Discussion On ISA Formal Spec
Cloud Atomic Laboratory: Why RISC-V?
DesignNews: 2019 Will Be The Year Of Open Source
EE Journal: Priming The RISC-V Pump
eeNews Europe: Feature-Rich RISC-V IDE Available For Free Trial
EE World: Shanghai To Increase Efforts To Support RISC-V Chip Development And Mass Production
eWEEK: Six Trends Experts See For Advancement Of RISC-V In 2019
Forbes: Digital Storage Projections For 2019, Part 2
Galios: 2018: Year in Review
GOWIN: GOWIN Semiconductor Licenses Intrinsic ID’s BroadKey To Deliver Hardware Root Of Trust For IoT Security
Hex Five Security: Hex Five’s Don Barnetson Joins RISC-V Foundation Marketing Committee As Co-Chair
Pact>: Western Digital RISC-V SweRV Core Is Now On GitHub
Phoronix: More Details On The Proposed Simple-V Extension To RISC-V For GPU Workloads
Rambus: India Tech Pursues RISC-V ISA
Rambus: The Next Vulnerability: Looking Back On Meltdown And Spectre One Year Later
Semiconductor Engineering: Building Security Into RISC-V Systems

December 2018: 
AB Open: Round-Table Discusses RISC-V, FOSSi Impact On Hardware Security
AB Open: OpenISA Launches New, Free RISC-V VEGAboard
All About Circuits: Building Out The RISC-V Ecosystem
All About Circuits: Western Digital SweRVs Towards Open Source With New RISC-V Core, ISS, And Cache Coherency
Andes Technology: Andes Custom Extension™ Further Accelerates Your High Performance RISC-V Processors
Antmicro: Renode 1.6 Released Making Linux-Enabled RISC-V Microchip PolarFire SoC Available To Everyone
Bluespec: Bluespec, Inc. Releases A Second Family Of Open-Source RISC-V Processors To Spur Open Innovation
Cadence: RISC-V: Real Products In Volume
CNX Software: Bluespec Flute Is A 5-Stage Open Source RISC-V Processor
CNX Software: BOOM Open Source RISC-V Core Runs On Amazon EC2 F1 Instances
Codasip: Mythic Chooses Codasip To Deliver RISC-V Computing In Their Revolutionary Neural Network Platform
Codasip: Codasip Releases Studio 8, A Breakthrough In RISC-V Automation, And The Bk7 RISC-V Processor Core For Real-Time Computing Applications
Codasip: Codasip Secures $10M In Series A Financing To Expand RISC-V Processor Technology Offerings
Dover Microsystems: Dover Microsystems’ Revolutionary Silicon IP Cybersecurity Approach Fuels Momentum
EE Journal: Microsemi Joins RISC-V Love Fest With SoC FPGA
EE Journal: RISC-V: The Groundswell Continues
EE Times: RISC-V Takes A Leap Forward
Electronic Design: Hard-Core RISC-V Cores Mate With FPGA
Electronics Weekly: IAR Systems And SiFive Collaborate On RISC-V
Embedded Computing Design: Embedded Insiders Tackle RISC-V Summit; Get Our Take On WD, NXP Announcements
Embedded Computing Design: RISC-V Has Officially Arrived
Embedded Computing Design: Imperas, Valtrix Partner For RISC-V Processor Verification
Embedded Computing Design: Andes RISC-V Cores Add Hex Five TEE To GOWIN FPGAs
Esperanto Technologies: Valtrix STING DV Platform Selected By AI Chipmaker Esperanto Technologies
Forbes: Digital Storage Projections For 2019, Part 1
Forbes: Western Digital Takes A RISC
Imperas: Imperas Expands Commercial Operations With Quantum Leap Sales For US Market Growth
Imperas: Imperas And Valtrix Announce Partnership For RISC-V Processor Verification
ITPro Today: RISC-V Summit Debuts To Showcase Open Source ISA
Microsemi: Industry’s First RISC-V SoC FPGA Architecture Brings Real-Time To Linux, Giving Developers The Freedom To Innovate In Low-Power, Secure And Reliable Designs
The Linley Group: Esperanto Maxes Out RISC-V
eeNews Analog: Mythic AI Adopts RISC-V Core From Codasip
Open Electronics: RISC-V, The Era Of Open Source CPU Has Begun
QuickLogic: QuickLogic CTO, Tim Saxe, To Present At The RISC-V Summit
Semiconductor Engineering: Beyond The RISC-V ISA
Semiconductor Engineering: Security And Open-Source RISC-V Hardware
SemiWiki.com: Imperas And RISC-V
SiFive: SiFive Recognized As Most Respected Private Semiconductor Company
SiFive: SiFive Announces Multiple Technical Advances At RISC-V Summit
Thales: IIT Madras To Partner With Digital Firm Thales To Design Shakti Processors With Highest Global Safety Critical Standard
UltraSoC: RISC-V Summit: Automotive Developments, System-Level Design, WD SweRV Core, And More…
UltraSoC: Systemic Complexity: Time For RISC-V To Rise To The Challenge
Western Digital: Western Digital Delivers New Innovations To Drive Open Standard Interfaces And RISC-V Processor Development

November 2018:
AB Open: Thales Joins RISC-V Foundation, Praises ISA’s Protection From “Cyber Threats”
Andes Technology: Andes Technology And INVECAS Announce Partnership To Win RISC-V-Based SoC Designs For Advanced Processes
DataCenter Knowledge: Open Source RISC-V Silicon Project And Linux Foundation Form Partnership
Dover Microsystems: Dover Microsystems Underscores Commitment to RISC-V Foundation
EE Journal: CPU Security Gets Hardcore
EE Times: RISC-V Momentum Seen Growing In China
eeNews Europe: Esperanto Raises Funds For AI Superchip
Electronics Weekly: Andes And IAR Systems Link On RISC-V
Electronics Weekly: SiFive Launches More Powerful RISC-V Core
Embedded Computing Design: Imperas RiscvOVPsim Brings Free, Open-Source Modeling And Simulation To RISC-V Ecosystem
Esperanto Technologies: Esperanto Technologies Secures $58 Million In Series B Investment For AI Chips
Esperanto Technologies: Moortec’s 7nm In-Chip Monitoring Subsystem IP Chosen By Esperanto Technologies To Optimize Performance And Reliability In Its High-Performance AI Chip
GreenWaves Technologies: GreenWaves Technologies Named Finalist For The 2018 Electronic Products’ “Product Of The Year Awards”
Hex Five Security: Hex Five Security Announces Creation Of Strategic Advisory Board
Hex Five Security: Hex Five Adds MultiZone Security To The Andes RISC-V Cores On GOWIN FPGAs
IAR Systems: IAR Systems And Andes Collaborate To Boost Performance For RISC-V Users
Imperas: Imperas Co-Hosting The First RISC-V Cambridge Meetup With UltraSoC
Imperas: Imperas Empowers RISC-V Community With riscvOVPsim
LinuxGizmos.com: This Under-$6 SBC Runs Linux On C-SKY ISA Chip
lowRISC: Tutorial For The v0.5 lowRISC Preview Release
Nervos: An Introduction To Nervos CKB-VM
New Electronics: UltraSoC Launches “Any Processor” Lockstep Solution For Safety-Critical Systems
Phoronix: The EOMA68 Libre Computer Developer Wants To Tackle A Quad-Core RISC-V Libre SoC Design
SemiWiki.com: SiFive Extends Portfolio With 7 Series RISC-V Cores
SiFive: SiFive Appoints VP To Growing SoC IP Group
SiFive: SiFive, Credo And Open-Silicon Showcase End-To-End Solutions For HPC And Networking Applications At SC18 In Dallas
Silex Insight: Silex Insight Joins RISC-V Foundation
SureCore: SureCore Joins The RISC-V Foundation
TechSpark: UltraSoC Hosts Bristol RISC-V Meetup As It Looks To Expand
Thales: Thales Joins RISC-V Foundation To Help Secure Open-Source Microprocessors
UltraSoC: UltraSoC Launches “Any Processor” Lockstep Solution For Safety-Critical Systems

October 2018:
AB Open: RISC-V Foundation Launches Soft CPU Design Contest
All About Circuits: Securing Embedded Processors on RISC-V
Andes Technology: Andes Announces Over 1.2 GHz RISC-V Cores Series At 28nm: A25/AX25 And N25F/NX25F
Andes Technology: Andes RISC-V CON Debuts At Hyatt Regency Santa Clara November 13; Linley Group, MediaTek, Andes, Faraday, GOWIN, Imperas Software, Hex Five, And XtremeEDA To Detail RISC-V Technology Advance
Andes Technology: GOWIN Semiconductor Licenses Andes Technology RISC-V CPU Core For Its Arora® GW-2A FPGA Family Products
CNX Software: $50 Kendryte KD233 Board Features K210 Dual Core RISC-V SoC
Codasip: Codasip Studio And Codasip Codespace 7.2 Available
ECN: Roundtable Part 1: Experts Discuss Current Trends And Future Obstacles
ECN: Roundtable Part 2: Experts Examine New Innovations And Share Advice For Future Engineers
Electronic Products & Technology: Hardware Root Of Trust Boosts RISC-V AI Application Processor
Electronics Weekly: UltraSoC Launches UltraDevelop 2 IDE
Embedded Computing Design: Hex-Five Multi-Zone Security For RISC V Simplifies The Terrible TEEs
EnterpriseTech: Penguin’s New Practice For Piecing AI Strategies Together
Esperanto Technologies: See Esperanto Technologies At The RISC-V Day Tokyo, October 2018
Hackaday: Programming A RISC-V Softcore With Ada
Netronome: Netronome Announces Open Chiplet Architecture For Advanced SoC Designs
NXP: NXP Selects Dover Microsystems’ State-of-the-Art CoreGuard Cybersecurity Technology for Future Embedded Platforms
Power Electronics: The Semiconductor Industry Is In Transition
Semiconductor Engineering: RISC-V Inches Toward The Center
Semiconductor Engineering: RISC-V: More Than A Core
SiFive: SiFive Welcomes Former Tesla Executive To Lead Global Growth Strategy
UltraSoC: UltraSoC And ResilTech Partner To Further Functional Safety In Automotive Systems
UltraSoC: UltraSoC Announces Integrated Multi-Core Debug, Visualization And Data Science / Analytics Suite

September 2018:
All About Circuits: RISC-V: All Hype Or Real Hope For The Processor Market?
Andes Technologies: Join Andes Technology Corporation At The TSMC Open Innovation Platform® Ecosystem Forum
Codasip: Codasip Expands Its Global Reach By Signing Channel Partnerships Throughout Asia
Computerworld: Data61 Partners With German Vendor To Protect Global Defense Systems
Embecosm: Supporting The RISC-V Vector Extension In GCC And LLVM
GreenWaves Technologies: GreenWaves Technologies Licenses Intrinsic ID Hardware Root Of Trust For RISC-V AI Application Processor
Hex Five Security: Hex Five Security Adds MultiZone™ Trusted Execution Environment To The SiFive Software Ecosystem
Imperas: RISC-V Custom Instruction Design And Verification Flow
Imperas: riscvOVPsim: A Complete RISC-V ISS For Bare-Metal Software Development And Specification Compliance Test Development
PULP Platform: PULP Platform Announces HERO: Open Heterogeneous Research Platform
Rambus: No Need To Reinvent The Wheel: How Easy It Is To Build With RISC-V
The Register: Arms Race: SiFive, Hex Five Build Code Safe Houses For RISC-V Chips
The Register: Boffins Are Building An Open-Source Secure Enclave On RISC-V
SiFive: SiFive And Open-Silicon Host The Final RISC-V Tech Symposium 2018 In New Delhi
SiFive: Wasiela Brings Encryption, FEC And Connectivity IP To DesignShare

For more ecosystem news, please visit: https://riscv.org/news/. The website is updated regularly and please share any coverage or news directly with Racepoint Global at: RIS…@racepointglobal.com to be included.

Welcome to our newest members!

 

 

 

 

 

Tags: