RISC-V Workshop Taiwan Proceedings

RISC-V Workshop Taiwan Proceedings

March 12-13, 2019

The RISC-V Workshop Taiwan took place from Tuesday, March 12 to Wednesday, March 13, 2019 at the Ambassador Hotel in Hsinchu City, Taiwan. RISC-V Workshop Taiwan showcased the open, expansive and international RISC-V ecosystem, highlighting current and prospective projects and implementations that influence the future evolution of the RISC-V instruction set architecture (ISA), with a focus on the growth of the RISC-V ecosystem across China and Asia.

The event featured a variety of speaking sessions, along with poster presentations and demonstrations. RISC-V Foundation member companies presenting at the Workshop including: Andes Technology; Codasip; Cryptape Technology; Hex Five Security; MediaTek; Microsemi, a wholly owned subsidiary of Microchip Technology Inc.; Nuclei System Technology; SiFive; Software Hardware Consulting (SH Consulting); Syntacore; and Western Digital.

Proceedings

Check out the slides and videos from each of the sessions below.

Tuesday, March 12, 2019 RISC-V Workshop Taiwan

 

Time Event Speaker, Affiliation Slides
8:00 Registration
8:55 Welcome Chih-Tsun Huang, National Tsing Hua University Slides | Video
9:00  Welcome & Foundation Overview Rick O’Connor, RISC-V Foundation SlidesVideo
9:15 Panel: Opportunities & Challenges in AIoT Frankwell Lin, Andes Technology; Steve Lo, Egis Technology Corp; Ted Speers, Microchip Technology; Chen-Yi Lee, National Chiao-Tung University; Zvonimir Bandic, Western Digital Slides | Video
10:00

Keynote: RISC-V: From Hype to Ripe

Charlie Su, Andes Technology Slides | Video
10:25 Networking Break
10:50 RISC-V Technical Committee Update Kevin Chen, Andes Technology Slides | Video
11:05 RISC-V Marketing Committee Update Ted Marena, RISC-V Foundation Marketing Committee and Western Digital Slides | Video
11:20 Status update of RISC-V P extension task group Chuan-Hua Chang, Andes Technology Slides | Video
11:35 Simulation Evaluation of Chaining Implementation for the RISC-V Vector Extension Zhen Wei, National Taiwan University Slides | Video
12:00 RISC-V Segmentation Extension Proposal Wuyang Chung, Freelancer Slides | Video
12:15 Lunch & Networking Break
13:15 MediaTek RISC-V Processor on Sensorhub Application Jeremy Liu and Shih-Han Lin, MediaTek Slides | Video
13:45 New Members of AndeStar V5 Processor IPs Charlie Su, Andes Technology Slides | Video
14:15 Our Passion on the Popularization of RISC-V Tony Xu, Nuclei System Technology Slides | Video
14:40 Networking Break & Tabletop Visit
15:05 Platform Security–A Detailed Comparison of RISC-V to ARM’s TrustZone Don Barnetson, Hex Five Security Slides | Video
15:35 CryptospeC: a Trust Module System for 64-bit RISC-V Core Complex Shumpei Kawasaki, SH Consulting; Cong-Kha Pham, University of Ellectro-Communication Slides | Video
16:05 Energy-Efficient Face Detection Using Andes RISC-V Processor Chien-Hao Chen and Po Yu Huang, National Chiao Tung University (NCTU) Slides | Video
16:20 A Different World: a Blockchain-Focused, General-Purpose Applicable Software Sandbox System Based on RISC-V Xuejie Xiao, Cryptape Technology Slides | Video
16:45 Enabling TVM on RISC-V Architectures with SIMD Instructions Allen Lu, Peakhills Group Corporation; Jenq-Kuen Lee, National Tsing-Hua University Slides | Video
17:10 Poster Preview Session: RISC-V Architecture Optimization through Extensible Instruction Sets and Custom Accelerators Wen-Cong Huang and Chia-Hsiang Yang, National Taiwan University Slides | Video
17:10 Poster Preview Session: Unbounded Formal Verification of RISC V CSRs with Interval Property Checking Nicolae Tusinchi, OneSpin Solutions Slides | Video
17:10 Poster Preview Session: Firmware Freedom: Coreboot for RISC-V Xiang Wang and Shawn Chang, TYA Information Technology Co., Ltd. Hardened Linux Community Slides | Video
17:10 Poster Preview Session: One Rocket Architecture-Based SoC Chip on 55nm Technologies and Its Future Evolution Yiqun Sun and Liling Kao, UC Tech IP Slides | Video
17:10 Poster Preview Session: Implementing 64-bit RISC-V Chip with MMU, L1 and L2 Memories Using Academic Shuttle in Japan Kesami Hagiwara, The University of Electro-Communications Slides | Video
17:10 Poster Preview Session: CloudBEAR Processor IP Product Line Alexander Kozlov, CloudBEAR Slides | Video
17:30 Networking Reception & Tabletop Visit

 

Wednesday, March 13, 2019 RISC-V Workshop Taiwan

 

Time Event Speaker, Affiliation Slides
8:00 Registration
9:00 Welcome Chih-Tsun Huang, National Tsing Hua University Slides
9:05

Securing a New Golden Age of Computer Architecture

Ted Speers, RISC-V Foundation and Microchip Technology Slides | Video
9:35 The Updated Status of RISC-V SW Kito Cheng and Greentime Hu, Andes Technology Slides | Video
10:05 RISC-V Perf Tool Status Alan Kao, Andes Technology Slides | Video
10:20 Linux on RISC-V — Fedora and Firmware Status Update Wei Fu, Red Hat Slides | Video
10:45 Networking Break & Tabletop Visit
11:15 Toolchain: Compiler Support for Linker Relaxation in RISC-V Shiva Chen and Hsiangkai Wang, Andes Technology Slides | Video
11:45 Toolchain: RISC-V Configurability in Compliance Test Framework Milan Skala, Codasip Slides | Video
12:15 Toolchain: Enhanced LLVM Support For RISC-V Zdenek Prikryl, Codasip Slides | Video
12:40 Networking Lunch & Tabletop Visit
14:10 Datacenter Processors with OmniXtend Interfaces for Shared Memory and AI Workload Acceleration Paul Loewenstein, Western Digital Slides | Video
14:55 PolarFire SoC FPGA — AMP Capable Solution for Both Deterministic Real-Time and Rich OS Support Vishakh Rayapeta, Microsemi Slides | Video
15:10 Enabling Embedded Intelligence Jack Kang, SiFive Slides | Video
15:40 SCRx Family of the RISC-V Compatible Core IP by Syntacore Alexander Redkin and Pavel Khabarov, Syntacore Slides | Video
16:05 Closing Session Chih-Tsun Huang, National Tsing Hua University Slides | Video
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