AB Open Article: Western Digital Boasts Of “Gratifying” SweRV Response, Releases FPGA Reference Design

Western Digital has announced a strong response to the release of its RISC-V based open silicon SweRV Core, along with the availability of an official implementation for field-programmable gate array (FPGA) use.

Announced back in December 2018 as part of a company-wide initiative to transition data processing products away from proprietary cores to alternatives based on the RISC-V instruction set architecture (ISA), released in January this year, and the subject of a deep-dive analysis by Tom Verbeure last month, Western Digital’s SweRV Core is provided under the Apache Licence 2.0 alongside a simulator dubbed Whisper and a cache coherency fabric.

 

To read more, please visit: https://abopen.com/news/western-digital-boasts-of-gratifying-swerv-response-releases-fpga-reference-design/.

Tags: