ASIC design services and IP R&D and sales vendor Zhiyuan released its RISC-V-based ASIC platform solution, which has been successfully applied to the design and mass production of next-generation terminal artificial intelligence and IoT SoC. The solution includes complete system level design services such as RISC-V core IP integration, SoC design verification, and a complete peripheral driver and RTOS reference design kit. Zhiyuan has assisted major customers in mass production of RISC-V Artificial Intelligence SoC in the UMC 55ULP process to meet the special performance requirements of wafers used in battery-powered IoT terminal devices.
Zhiyuan’s chief operating officer, Lin Shiqin, said that the Chihiro RISC-V ASIC solution, which has been mass-produced, can create a competitive SoC design for customers and outline the unique SoC in the rapidly growing RISC-V market. In particular, we have seen many RISC-V ASIC design opportunities in a variety of terminal AI, IoT/AIoT and networking applications. Zhiyuan hopes to realize more innovative designs to create benefits for customers and the market.
To read more, please visit: https://www.chinatimes.com/realtimenews/20190410001223-260410?chdtv. Please note that the original article is in Chinese.