Andes has upgraded its A25 and AX25 RISC-V CPUs, adding cache-coherent multicore support in the new MP models along with an optional DSP extension. The designs implement the AndeStar V5 ISA, which is a superset of RISC-V. The A25 is compatible with RISC-V’s 32-bit RV32 ISA, and the 64-bit AX25 is compatible with RV64. They employ the same architecture as the company’s N25 and NX25, respectively, but add an MMU to run Linux.
To read more, please visit: https://www.linleygroup.com/newsletters/newsletter_detail.php?num=6002 Copyright © 2019 The Linley Group