The Linley Group Article: Andes Strengthens Its RISC-V Arsenal

Andes has upgraded its A25 and AX25 RISC-V CPUs, adding cache-coherent multicore support in the new MP models along with an optional DSP extension. The designs implement the AndeStar V5 ISA, which is a superset of RISC-V. The A25 is compatible with RISC-V’s 32-bit RV32 ISA, and the 64-bit AX25 is compatible with RV64. They employ the same architecture as the company’s N25 and NX25, respectively, but add an MMU to run Linux.

The new multicore option allows customers to integrate the A25MP and AX25MP in cache-coherent clusters of two or four cores. In 28HPC+ technology, the CPUs can run SMP Linux at over 1.2GHz, but the worst-case specification is 1.0GHz.


To read more, please visit: