The roadshow will feature live demonstrations and presentations from RISC-V Foundation members, includes free admission
WHAT: The RISC-V Foundation has announced the agenda for its “Getting Started with RISC-V” events across Europe and the Middle East.
WHERE: Tel Aviv, Israel; Munich, Germany; Berlin, Germany; Tallinn, Estonia; Paris, France; London, United Kingdom.
WHEN: Monday, Sept. 16 to Thursday, Sept. 26, 2019
DETAILS: The RISC-V Foundation, in collaboration with the Linux Foundation, is hosting a series of free, half-day “Getting Started with RISC-V” events. These seminars will feature RISC-V Foundation members including Adacore, Andes Technology, GreenWaves Technologies, Microchip Technology, Minres Technologies, OneSpin Solutions, Syntacore, Thales, Trinamic Motion Control and Western Digital. Additional companies are also expected to join at specific locations. RISC-V Foundation members will give presentations and live demonstrations showcasing innovation RISC-V solutions and implementations. Attendees will learn about the RISC-V ecosystem’s increasing footprint in EMEA and beyond.
Getting Started with RISC-V Agenda
- Registration & Breakfast
- When: 8:30 – 9:00
- Introduction to RISC-V
- When: 9:00 – 9:20
- Who: RISC-V Foundation
- Rocinante: Motor Control SoC with Integrated RISC-V Core
- When: 9:20 – 9:40
- Who: Trinamic Motion Control
- SweRV Core & CHIPS Alliance Initiatives
- When: 9:40 – 10:00
- Who: Western Digital
- SCRx Family of the RISC-V Processor IP
- When: 10:00 – 10:20
- Who: Syntacore
- Morning Break
- When: 10:00 – 10:50
- Machine Learning on Battery Operated Devices at the Very Edge Using a Multi-core RISC-V Based Processor
- When: 10:50 – 11:10
- Who: GreenWaves Technologies
- RISC-V SoC FPGA Brings Real-Time to Linux
- When: 11:10 – 11:30
- Who: Microchip Technology
- Fast Start into RISC-V for AIoT with A+ Core
- When: 11:30 – 11:50
- Who: Andes Technology
- When: 11:50 – 13:00
- Embedded Software Development for RISC-V Based SoC
- When: 13:00 – 13:20
- Who: Minres Technology
Program is subject to change in advance of the roadshow. Each event is admission free, see below to register.
- Tel Aviv: Monday, Sept. 16 at the Dan Tel Aviv Hotel – please register here.
- Munich: Wednesday, Sept. 18 at the Hilton Munich Park – please register here.
- Berlin: Thursday, Sept. 19 at the Courtyard Berlin City Center – please register here.
- Tallinn: Monday, Sept. 23 at the Hilton Tallinn Park – please register here.
- Paris: Tuesday, Sept. 24 at the Station F – please register here.
- London: Thursday, Sept. 26 at the Etc.Venues – Fenchurch Street – please register here.
To learn more about the RISC-V European Roadshow, please visit: https://events.linuxfoundation.org/events/risc-v-europe-roadshow-2019/
In addition to the seminars, Thales and Microchip Technology are sponsoring the RISC-V Soft CPU Contest to advance the development of secure RISC-V solutions. Winners will be announced at the “Getting Started with RISC-V” event in Paris on Sept. 24.
For press interested in attending and scheduling meetings with the RISC-V Foundation and member companies, please email: firstname.lastname@example.org.
To learn more about the RISC-V Foundation, its open, free architecture and membership information, please visit: https://riscv.org.
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 275 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.