How the European Processor Initiative is Leveraging RISC-V for the Future of Supercomputing

By Calista Redmond, CEO of the RISC-V Foundation

We wanted to shine a spotlight on the European Processor Initiative (EPI), the project financed under the EU Horizon 2020 program, which has gathered together 26 partners from 10 European countries with the mission to develop and bring to market low power processor technology. The EPI consortium includes RISC-V Foundation members Barcelona Supercomputing Center (BSC), CEA, ETH Zurich, FORTH, Infineon and STMicroelectronics. The EPI project includes experts in the silicon and High Performance Computing (HPC) industries are collaborating to develop the first European HPC system-on-chips (SoCs) and accelerators, with the goal of creating a processor for the Exascale machine based on European technology. This Exascale supercomputer will be capable of one exaflop of performance –around a million times faster than typical desktop computers – which has the potential to significantly advance AI and scientific research.

When the EPI Consortium was approved in May 2018, European Commission leaders proclaimed that the project will help “develop an independent and innovative European supercomputing and data ecosystem” and “benefit Europe’s scientific leadership, industrial competitiveness, engineering skills and know-how and the society as whole.” In addition to focusing on solutions for the HPC market, the EPI project also targets the autonomous vehicles industry and the data center and servers market. As processing demands for these applications are skyrocketing – for example, as cars become more autonomous and capable of real-time decision making – novel silicon approaches are required to power the next generation of smart devices and machines.  

As part of the EPI project, the Accelerator stream is working to develop and demonstrate European processor IPs based on the RISC-V instruction set architecture (ISA). The accelerator will be designed for high throughput and power efficiency within the general purpose processor (GPP) chip. The EPI explains that using RISC-V enables the program to leverage “open source resources at [the] hardware architecture level and software level, as well as ensuring independence from non-European patented computing technologies.”

For more background on the EPI, check out the program’s website. You can also watch the keynote from BSC Director Prof. Mateo Valero at the 2018 RISC-V Workshop in Barcelona and view the presentation. To read more about the latest solutions developed by the EPI, check out news on the EPI website and the recent coverage from The Next Platform and Tom’s Hardware.

Bringing the industry a new level of free, extensible software and hardware freedom on architecture, the RISC-V ISA is opening up exciting new possibilities for innovation – especially for segments like HPC and AI that are undergoing compute disruption. The RISC-V Foundation has many work groups to further the open source technical progress of the ISA, including many key elements related to HPC. In addition, we have a Special Interest Group dedicated to collaboration of HPC interests. To learn more, please email hpc@riscv.org.

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