The self-developed RISC-V open-source chip design system-level verification and prototype platform SERVE was officially released. It was recently debuted at the 23rd Annual Conference of Computer Engineering and Technology of the Chinese Computer Society, and the 9th “Microprocessor Technology” Forum.
According to the China Open Instruction Eco-RISCV Alliance, the SERVE platform is based on the mainstream SoC-FPGA programmable logic devices and boards currently on the market. Compared with the existing RISC-V FPGA system-level verification platform, the SERVE platform implements RISC-V.
To read more, please visit http://news.hqew.com/info-350175. Please note that the article is in Chinese.
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