As the number of connected devices skyrockets, the attack surface also increases. To solve the growing challenge of mitigating cybersecurity threats, every component in a system must be evaluated for its vulnerabilities. Processors today are able to run billions of instructions per second – this means you can access a world of content at your fingertips, but there’s also a risk of exploitation. Every processor requires built-in security features to keep systems safe.
A few months ago, we launched the RISC-V Soft CPU contest sponsored by RISC-V Foundation members Microchip Technology and Thales. Designers were challenged to develop a hardware secure RISC-V soft CPU solution that could thwart malicious software security attacks. The contest showed that simple mitigations can be integrated into designs to provide improved security. The contest also highlighted how the simple and flexible RISC-V architecture is ideal for securing the IoT. You can read about the rules of the contest at GitHub.
At the RISC-V EMEA Roadshow event in Paris on Sept. 24, Bertrand Tavernier of Thales announced the RISC-V Soft CPU contest winners. Each of the winning projects successfully mitigated five classical security attacks. Read on to learn more about the winning entries:
First place: Changyi Gu scored 78/100 for Rattlesnake, winning 5000€, a HiFive Unleashed and a HiFive Unleashed Expansion Board. In addition to having the fastest implementation, the entry also stood out for its creativity and the quality of the documentation. Changyi implemented a sophisticated dirty bit method where consecutive suspicious writes are tagged, even when used indirectly. When an attacker tries to execute tagged memory, the processor stops the execution immediately. This method is a very good tradeoff between efficiency and complexity. Check Changyi’s entry here: https://github.com/PulseRain/Rattlesnake.git
Second place: Matthew Ballance scored 73/100 for the Featherweight RISC-V (FWRISC-S), winning 2000€ and a HiFive Unleashed. In a very compact processor Matthew implemented a data execution prevention scheme where the defined memory area is protected until the next core reset. The compactness of the design was quite impressive. Check out Matthew’s entry here: https://github.com/mballance/fwrisc-s
Third place: Jörg Mische scored 69/100 for his RudolV RISC-V processor, winning 1000€ and a HiFive Unleashed. The design defines a memory region where execution of code is forbidden when associated to suspicious memory writes detection. Check out Jörg’s entry here: https://github.com/bobbl/rudolv
We would like to give a special shout-out to the Ecco team, made up of Alexey Baturo, Anatoly Parshintsev, Fedor Veselovsky, Igor Chervatyuk and Sergey Matveev. The Ecco team developed a RISC-V processor implementing memory tagging using a pseudo-random generator. They also tuned the toolchain to tightly cooperate with the processor. Starting from the SPU32 processor, they showcased how RISC-V can enable anyone to work at a hardware level, even a team made up of software engineers. While the Ecco team’s solution ran on a different board than outlined by the contest rules (and was thus ineligible to win), we appreciate all their hard work. RISC-V is truly breaking down the barriers between software and hardware for the benefit of everyone. Check out the Ecco team’s entry here: https://github.com/spacemonkeydelivers/riscv_security_contest_project
Thanks again to everyone who participated and shared their feedback on the contest!