The RISC-V Instruction Set Manual describes the current status of the RISC-V ISA and its extensions. Among these there’s a mention of the ‘B’ extension that is meant to host specific instructions for bit manipulation operations.
A well known proposal for such extension comes from Clifford Wolf and can be found here.
We implemented an extension of the RISC-V back end of LLVM based on such proposal that is now available on the Embecosm GitHub repository: https://github.com/embecosm/llvm-project
Our work is being presented as a poster at the LLVM Developers Meeting 2019, at the San Jose Convention Center, San Jose, CA.