This first episode of OpenHW TV is focused on the Verification of CORE-V open source RISC-V processor IP cores. Guests include the new Co-Chairs of the OpenHW verification task group (Futurewei and SiliconLabs) with contributing members Imperas and Metrics highlighting the open source CORE-V processor IP Design Verification (DV) plan using state of the art flows and SystemVerilog UVM test-benches with encapsulated Imperas RISC-V reference model, coverage based flow, and Metrics flexible cloud based environment. Following the updates and presentations by Imperas and Metrics all the panellist will be available for the live Q&A session with audience participation.
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