RISC-V International – RISC-V: The Open Standard RISC Instruction Set Architecture

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Upcoming Event

RISC-V Summit Europe

The RISC-V Summit Europe is the premier event that connects the European movers and shakers - from industry, government, research, academia and ecosystem support - that are building the future of innovation on RISC-V. Join us in Munich from June 24-28 to be part of the new wave of European computing innovation!

Technical

Specifications

The RISC-V instruction set architecture (ISA) and related specifications are developed, ratified and maintained by RISC-V International contributing members within the RISC-V International Technical Working Groups. Work on the specification is performed on GitHub, and the GitHub issue mechanism can be used to provide input into the specification.

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Landscape

Accelerating and Building the Strongest Ecosystem

The RISC-V Ecosystem Landscape is a living document that developers, investors, vendors, researchers and others can use as a resource on the ecosystem supported by RISC-V.

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Blog

Brazil and Europe Sign Innovative Project with RISC-V Technology for HPC

An international collaboration will enable Brazil to develop RISC-V technologies to accelerate research and development in the areas of semiconductors and supercomputing in the country. This innovative project marks the beginning of the journey towards developing a Matrix Multiplication Acceleration Unit, integrated into a RISC-V processor.

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In The News

Understanding RISC-V: The Open Standard Instruction Set Architecture

With a groundbreaking open-source architecture, RISC-V is paving the way for a new era of computing technology. In this article, we’ll delve into RISC-V’s evolution, its underlying principles and technical aspects, as well as its limitations and future prospects.

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RISC-V International comprises a large member organization building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Through various events and workshops, RISC-V International is changing the way the industry works together and collaborates – creating a new kind of open hardware and software ecosystem. Become a member today and help pioneer the industry’s future de facto ISA for design innovation.

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RISC-V Blog

Introducing SoM1-SOC: The Most Powerful SoM Based on PolarFire® SoC FPGA

RISC-V Community News | Blog | No Comments

By: Mans Ahmadian, Senior Design Engineer at Sundance DSP In this blog post, we will discuss the features, benefits and applications of SoM1-SOC, a powerful system-on-module (SoM) based on PolarFire® System-on-Chip…

Integrated IP Core Generation Workflow for Microchip SoC FPGAs With MathWorks®

RISC-V Community News | Blog | No Comments

By: Puneet Kumar Learn more about IP Core Generation workflow from MATLAB® R2022A release onwards for PolarFire® SoC FPGA and SmartFusion® 2 family of Microchip FPGAs. Introducing IP Core Generation for PolarFire SoC and SmartFusion 2…

In the News

RISC-V: Democratizing Innovation in CPU Design

RISC-V Community News | In the News | No Comments

RISC-V has emerged as a groundbreaking force in the semiconductor industry, fundamentally changing the CPU design and manufacturing landscape. By providing an open standard instruction set architecture (ISA), RISC-V has…

BSC and Brazil’s Instituto ELDORADO Collaborate to Advance RISC-V Development for HPC and AI

RISC-V Community News | In the News | No Comments

An international collaboration between BSC and Instituto ELDORADO will enable Brazil to develop open-source RISC-V technologies to accelerate research and development in the areas of semiconductors and supercomputing. The primary goal of this project…