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The RISC-V Foundation Announces Agenda for the Second Annual RISC-V Summit

By October 15, 2019October 1st, 2020No Comments

The three-day conference will feature keynotes, exhibitions, smaller breakout sessions, tutorials and networking receptions
WHAT: The RISC-V Foundation has announced the agenda for the RISC-V Summit 2019
WHERE: San Jose Convention Center in San Jose, Calif.
WHEN: Monday, Dec. 9 to Thursday, Dec. 12, 2019
DETAILS: The RISC-V Foundation, in partnership with Informa’s Tech Division of Informa PLC, is hosting its annual RISC-V Summit, a four-day conference featuring keynotes, smaller breakout sessions, tutorials, exhibitions and networking receptions, as well as member meetings to open the week’s events. Leading technology companies and research institutions will share notable product updates, projects and implementations and discuss how the RISC-V ISA is driving the next generation of hardware, software and IP. The keynotes for the RISC-V Summit will include representatives from Arm, IBM, Microchip, OpenHW Group, SiFive and Western Digital. 
 RISC-V Summit activities are as follows:

  • Monday, Dec. 9, 2019 – Only open to RISC-V Foundation member companies.
  • Tuesday and Wednesday, Dec. 10-11, 2019 – The main conference will take place on these two days, with keynotes in the morning followed by breakout sessions and networking events.
  • Thursday, Dec. 12, 2019 – The last day of the RISC-V Summit will include technical tutorials, highlighting RISC-V  implementations across a variety of industries. 

Below is the preliminary agenda. For the latest agenda updates and schedule, please visit:
Tuesday, Dec. 10, 2019 RISC-V Summit Agenda

Time (PST) Event Speaker, Affiliation
8:00 a.m. Registration is open from 8:00 a.m. – 7:00 p.m.  
9:00 a.m. Welcome Address Calista Redmond, RISC-V Foundation
9:20 a.m. State of the Union + Work Group Updates Krste Asanovic, UC Berkeley & SiFive
10:00 a.m. Keynote Martin Fink, Western Digital
10:20 a.m. Open for Business: Trues Stories of How Far We’ve Come With the RISC-V Ecosystem Ted Speers, Microchip Technology Inc.
10:40 a.m. Lighting Talks  
10:50 a.m. Keynote  
11:10 a.m. Taking RISC-V Into New Markets Yunsup Lee, SiFive
11:30 a.m. Expo Hall is open from 11:30 a.m. – 7:00 p.m.  
11:30 a.m. Lunch Break  
12:50 p.m. Code Size of RISC-V Versus ARM Using Embench™ 0.5 Benchmark Suite: What is the Cost of ISA Simplicity? David Patterson, RISC-V Foundation
12:50 p.m. Linux on RISC — Fedora and Firmware Status Update Wei Fu, Red Hat
12:50 p.m. Headline Sponsor Session with Western Digital Western Digital
1:20 p.m. Every CPU Cycle Counts Gajinder Panesar &  Iain Robertson, Ultra SOC
1:20 p.m. Architectural Extensions for a RISC-V Processor for Embedded Security Tariq Kurd, Huawei UK
1:20 p.m. Headline Sponsor Western Digital Presents: GCC Compiler: Code Size Density Ofer Shinaar, Western Digital
1:20 p.m. Emerald Sponsor Session with Microchip  
1:50 p.m. A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing Zdenek Prikryl, Codasip
Hela Belhadj Amor, LETI
1:50 p.m. System-Level Security Verification of RISC-V Based SoCs Nicole Fern, Tortuga Logic, Inc.
1:50 p.m. Open Source Compiler Tool Chains for RISC-V: Past, Present and Future Jeremy Bennett, Embecosm
2:00 p.m. Software PPA Metrics: Results from Real-world MCU Security Applications Joe Circello, NXP Semiconductors, N.V.
2:20 p.m. An Open and Coherent Memory Centric Architecture Enabled by RISC-V Dejan Vucinic &  Marjan Radi, Westen Digital
2:20 p.m. Ruby Sponsor Session with SiFive  
2:50 p.m. Software Flow for Complex SoC-FPGA Cyril Jean, Microsemi, a Microchip company
2:50 p.m. The RISC-V Journey Thru Containers to the Cloud Carlos Eduardo de Paula, Red Hat
3:10 p.m. Networking Break  
3:40 p.m. Avoiding Amdahl’s Law: RISC-V Architecture Exploration for AI & ML Many-core Compute Arrays Simon Davidmann, Imperas
3:40 p.m. High Assurance Cores through Formal Verification Muralidaran Vijayaraghavan, SiFive
3:40 p.m. Developing with FreeRTOS and RISC-V Richard Berry, FreeRTOS | Amazon Web Services
3:50 p.m. Scalable, Configurable Neural Network Accelerator Based on RISC-V Core Karthik Wali, LG Electronics
4:10 p.m. Enabling the Full Power of a Multiprocessor SoC Jeff Hancock, Mentor, A Siemens Company
4:10 p.m. Open Source Verification Platform for RISC-V Processors Richard Ho and Tao Liu, Google
4:10 p.m. Next-generation IDE for your RISC-V Product in 20 Minutes Ivan Kravets, PlatformIO
4:40 p.m. Coming Soon  
4:40 p.m. Democratising Formal Verification of RISC-V Processors Ashish Darbari, Axiomise Limited
4:40 p.m. Session Title to Come  
5:10 p.m. The Next Generation of GAP8: An IoT Application Processor for Inference at the Very Edge Martin Croome, GreenWaves Technologies
5:10 p.m. Formal Methods for Hardware-software Integration on RISC-V Embedded Systems Adam Chlipala  and Samuel Gruetter, MIT
5:10 p.m. Session Title to Come  
5:30 p.m. Welcome Happy Hour  

Wednesday, Dec. 11, 2019 RISC-V Summit Agenda 

Time (PST) Event Speaker, Affiliation
8:00 a.m. Registration is open from 8:00 a.m. – 5:30 p.m.  
8:30 a.m. Welcome  
8:35 a.m. Keynote  
8:55 a.m. Keynote  
9:15 a.m. Keynote  
9:35 a.m. Keynote  
9:55 a.m. Open Source Processor IP for High Volume Production SoCs: CORE-V Family of RISC-V Cores Rick O’ Connor, OpenHW Group
10:15 a.m. Lightning Talks  
10:25 a.m. Keynote Panel: Opportunity and Risks in Open Source Hardware Tim Whitfield, Arm
Mendy Furmanek, IBM
Brandon Lewis, Open Systems Media
Krste Asanovic, UC Berkeley and SiFive
11:10 a.m. Keynote  
11:30 a.m. Expo Hall  
11:30 a.m. Lunch Break  
12:50 p.m. Enabling AI on Low Power Endpoint Devices Utilizing the QuickLogic and SiFive Freedom Aware Templates Brian Faith, QuickLogic Corporation
12:50 p.m. RISC-V and a Meta-framework Security Certification Approach for a Secure Connected World John Boggie, NXP Semiconductors
12:50 p.m. RISC-V Software State of the Union Palmer Dabbelt, SiFive
1:20 p.m. A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing Zdenek Prikryl, Codasip
Hela Belhadj Amor, Univ. Grenoble Alpes, CEA, LETI
1:20 p.m. Production-ready RISC-V Support in LLVM/Clang 9.0 – How we Got There and What’s Next Alex Bradbury, lowRISC CIC
1:20 p.m. Session Title to Come  
1:50 p.m. SweRV Cores Roadmap Zvonimir Bandic, RISC-V Foundation, Next Gen Platform Technologies, Western Digital
1:50 p.m. Modeling a State Machine Security Monitor for RISC-V Architecture James Ross & Patrick Jungwirth, US Army Research Lab
1:50 p.m. Session Title to Come  
2:20 p.m. Panel Session: Processor IP Showcase  
2:20 p.m. RISC-V Enclaves: A Clean Slate Approach To Linux Security Cesare Garlati, Hex Five Security
2:20 p.m. Integrate RISC-V to build Open Common Automotive Platform Tiejun Chen, VMware
2:30 p.m. RISC-V: A New Zero-Trust Model for Cyber Resilient Avionics Kevin Kinsella, Northrop Grumman
2:50 p.m. Code Density Improvements Beyond The C Standard Extension Christian Jones & Zdenek Prikryl, Codasip
3:00 p.m. Debugging on Homogeneous and Heterogeneous Multicore SoCs Containing a Mix of RISC-V and non-RISC-V Cores Hugh O’Keeffe & Roisin O’Keeffe, Ashling
3:10 p.m. Networking Break  
3:40 p.m. Innovation in CPU Architecture, Pushing Data from Edge to Cloud Caffrey Chen, Alibaba
3:40 p.m. RISC-V Processor Verification based on Open-source Framework and State-of-the-art Cloud-based Methodologies Lee Moore, Imperas
Richard Ho, Google
3:40 p.m. Headline Sponsor Western Digital presents: RISC-V Hypervisor Support Alistair Francis &  Anup Patel, Western Digital
3:40 p.m. Session Title to Come  
4:10 p.m. Andes RISC-V Processor Solutions: From MCU to Datacenters Charlie Su, Andes Technology Corporation
4:10 p.m. Working Towards a Common C Library for Small RISC-V Systems Keith Packard, Altus Metrum, LLC
4:10 p.m. Session Title to Come  
4:40 p.m. Ara 2.0: 64-bit RISC-V Vector Processor in 22nm FD-SOI Matheus Cavalcante, ETH Zurich
4:40 p.m. Verifying RISC-V Vector and Bit Manipulation Extensions using STING Design Verification Tool Shubhodeep Choudhury, Valtrix
4:40 p.m. RISC-V For Heterogeneous Computing Zhipeng Huang, Huawei
5:10 p.m. Prototyping RISC-V Based Heterogeneous Systems-on-Chip with the ESP Open-Source Platform Luca Carloni, Columbia University
5:10 p.m. An Efficient Runtime Validation Framework based on the Theory of Refinement Mitesh Jain, Synopsys Inc.
Pete Manolios, Northeastern University
5:10 p.m. SafeRV: Building Blocks for Safety Critical RISC-V Systems Neel Gala, InCore Semiconductors Pvt. Ltd.
Daniel Gracia Pérez, Thales

Thursday, Dec. 12, 2019 RISC-V Summit Agenda

Time (PST) Event Speaker, Affiliation
8:00 a.m. Registration is open from 8:00 a.m. – 1:00 p.m.  
9:00 a.m. RISC-V Verification for Processor Cores and Optional Custom Extensions Richard Ho, Google
Lee Moore & Simon Davidmann, Imperas
Doug Letcher, Metrics Technologies, Inc.
9:00 a.m. A Tour of the RISC-V ISA Formal Specification Rishiyur Nikhil, Bluespec, Inc.
9:00 a.m. Fomu: Python, RISC-V, and FPGA in your USB Port Michael Gielda, Antmicro
Tim Ansell, Google
10:45 a.m. Designing and Building Modern Modular SoCs using Open-Source Federation Tools Jack Koenig, SiFive
10:45 a.m. An Introduction to RISC-V Boot Flow Atish Patra &  Anup Patel, Western Digital
11:45 a.m. Lunch Break  
1:00 p.m. GNU CGEN for RISC-V Tool Chain Customization Ed Jones, Embecosm
Mary Bennett, University of Surrey
1:00 p.m. seL4 on RISC-V Renode Jesse Millwood, DornerWorks
1:00 p.m. Chipyard and FireSim: End-to-End Architecture Exploration with RISC-V SoC Generators, FPGA-Accelerated Simulation and Agile Test Chips Borivoje Nikolic, UC Berkeley
2:15 p.m. How to Secure a RISC-V System in 90 minutes – From Single Core MCU to Mixed Criticality SMP Linux Cesare Garlati, Hex Five Security
Sandro Pinto, Universidade do Minho

The Summit’s Exhibit Hall will be open at the following times to showcase RISC-V-based product demonstrations and allow attendees to explore the latest innovations in the market: 
Tuesday, Dec. 10, 2019:

  • 11:30 a.m. – 7:00 p.m. PST 

Wednesday, Dec. 11, 2019:

  • 11:30 a.m. – 4:00 p.m. PST

Please note promotional pricing for the three-day Conference and Exhibition Pass is available until Friday, Oct. 18, 2019. Platinum, Gold and Silver level members of the RISC-V Foundation qualify for discount codes.  To learn more about the packages and limited-time promotions, please visit:
 Sponsorship packages and exhibition packages are also available, see details here. For press interested in attending, please email: to receive your complimentary pass.
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 325 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.

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