RISC-V Foundation Board of Directors

Krste Asanovic – Chairman of the Board

krstemitKrste Asanović is a Professor in the EECS Department at the University of California, Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005, before returning to join the faculty at Berkeley in 2007. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently Director of the Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending. He leads the free RISC-­V ISA project at Berkeley, is Chairman of the RISC­-V Foundation, and has recently co­founded SiFive Inc. to support commercial use of RISC­-V processors. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.

Zvonimir Bandic

ZZBandic2Zvonimir Z. Bandić is the Research Staff Member and Senior Director of Next Generation Platform Technologies in a Western Digital Corporation in San Jose, California. He received his BS in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and his MS (1995) and PhD (1999) in applied physics from Caltech, Pasadena, in the field of novel electronic devices based on wide bandgap semiconductors. He is currently focusing on both NAND and emerging Non-Volatile Memories (PCM, ReRAM, MRAM) applications for data center storage and computing, including CPU, memory, networking and storage. He has been awarded over 50 patents in the fields of solid state electronics, solid state disk controller technology, security architecture and storage systems and has published over 50 peer-reviewed papers.

Charlie Hauck

CHauck-RISC-VCharlie is CEO of Bluespec, Inc., provider of high­level tools and IP for ASIC and FPGA design. Before Bluespec, he was GM of Faraday Technology USA, a fabless ASIC company. Charlie has over 25 years of experience in marketing and developing RISC processors at Lexra, LSI Logic, Kendall Square Research and Commodore. Charlie received a Bachelor of Science from the Johns Hopkins University and a Master of Science from the Massachusetts Institute of Technology.

 

 

David Patterson

DaveLasVegas2011CloseupDavid Patterson is likely best-known for the book Computer Architecture: A Quantitative Approach written with John Hennessy or for Berkeley research projects Reduced Instruction Set Computers (RISC), Redundant Arrays of Inexpensive Disks (RAID), and Network of Workstations. He also served as Berkeley’s CS Division Chair, the Computing Research Association Chair, and President of the Association for Computing Machinery and was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He received the Berkeley Citation in 2016, which is given to distinguished individuals who go beyond the call of duty and whose achievements exceed the standards of excellence in their fields.

Jothy Rosenberg

Jothy RosenbergJothy Rosenberg has a PhD in computer science from Duke University where he initially also taught before heading off to be a serial entrepreneur. Between Silicon Valley, Boston and Portland, OR, Jothy has been a founder of eight high tech startups, two of which so far have been new processor companies. Currently, Jothy is associate director of the cyber security group at Draper Laboratories in Cambridge, MA. There he leads the Dover Inherently Secure Processing effort where they are using the RISC­-V ISA as the base for a processor that is immune to large classes of the worst types of network­ based attacks. Jothy is also on the boards of several other non­profits.

Frans Sijstermans

Frans SijstermansFrans Sijstermans is a vice president of engineering at NVIDIA. He is responsible for the architecture and implementation of the multi media hardware components, including camera interface, video codecs, image processing and computer vision accelerators, and display controller. Besides multimedia, his interests include processor architectures, deep learning, and security. He holds a MSc degree from the Eindhoven University of Technology, The Netherlands.

Ted Speers

Ted SpeersTed Speers is Head of Product Architecture and Planning for Microsemi’s SoC Group, responsible for defining their roadmap for low power, secure, reliable FPGAs and SoC FPGAs. He joined Microsemi in 1987 and held roles in process engineering and product engineering before assuming his current role in 2003. He is a Technical Fellow and co-inventor on 35 US Patents. Prior to joining Microsemi, he worked at LSI Logic. Ted has a BS in Chemical Engineering from Cornell.