TestRIG (Testing with Random Instruction Generation) is a testing framework for RISC-V implementations. The RISC-V community has standardized a formal model of the architecture in the Sail language, giving a…
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By: Francisca Tan, Product Management Lead – Tessent Embedded Analytics Siemens’ longstanding and deep engagement with the RISC-V community dates back to the foundation’s early days. Involved initially as the…
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Introduction Following the gap analysis done in the second half of 2023, the Vector Special Interest Group (SIG-Vector) has been working on specifying instructions to accelerate matrix operations. Two Task…
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Yang Li, Alibaba DAMO Academy Chromium, the most widely adopted open-source browser engine, serves as the foundation for numerous mainstream applications, including Chrome, Electron, VSCode, and WebView. As a critical…
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2024 has been a year of great technical progress for the RISC-V ISA. Our 75 Committees and Groups, staffed by contributors from RISC-V member organizations worldwide, work together to advance…
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As 2024 comes to a close, it’s clear that this has been a transformative year for RISC-V. From achieving industry firsts to driving innovation across industries like AI, automotive, and…
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S2C Launches Prodigy S8-100 Series: 100M Gate FPGA Prototyping for AI and HPC December 19, 2024 – S2C, a global leader in FPGA-based prototyping solutions, announces its Prodigy S8-100 Logic…
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Tammo Mürmann has just commenced his PhD studies at the Technical University of Darmstadt as part of the Embedded Systems and Applications Group (ESA). During his studies, he already participated…
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by Linda Njau, RISC-V Mentee at Ventana Micro SystemsI came across the Linux/RISC-V mentorship while searching for an internship, and my curiosity was sparked by the RISC-V standard and the…
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Weitong Su, Alibaba DAMO Academy Co-processors are specialized units designed to assist the main processor in executing specific tasks, such as graphics processing and signal transmission. By working in parallel…
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