RISC-V Design Contest Calls On Embedded Designers To Push The Limits Of Innovation

RISC-V SoftCPU Contest, sponsored by Google, Antmicro and Microchip, encourages designers to tinker with FPGA solutions based on the free and open RISC-V ISA Berkeley, Calif. – Oct. 8, 2018 – The RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced the call for submissions for the RISC-V SoftCPU Contest. The aim…

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RISC-V Ecosystem Highlights Innovative RISC-V Projects at RISC-V Day Tokyo

RISC-V members to present on RISC-V based products and solutionsWHERE: Keio University, Fujiwara Hall in the Kyosei Building at the Hiyoshi Campus, 4-1-1 Hiyoshi, Kohoku-Ku, Yokohama, Kanagawa, Japan, 223-8526WHEN: Thursday, Oct. 18, 2018 from 8:00 to 19:00 JSTWHAT: The RISC-V Foundation will share updates on new projects and implementations from its international membership at RISC-V Day Tokyo, with a focus on current and prospective RISC-V projects and implementations. This event…

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RISC-V Foundation Announces The Agenda For Its Inaugural RISC-V Summit

The RISC-V Foundation, a nonprofit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced the agenda for its first annual RISC-V Summit at the Santa Clara Convention Center in Santa Clara, Calif., taking place Dec. 3-6, 2018. The Summit, in partnership with Informa’s Knowledge & Networking Division, KNect365, will gather the RISC-V ecosystem for a multi-track technical…

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Agenda For RISC-V Day Tokyo on Oct. 18

RISC-V Day Tokyo Agenda Oct. 18, 2018 RISC-V Day Tokyo will be a single-day event on Thursday, Oct. 18 that will feature presentations and keynotes highlighting the RISC-V ecosystem’s growth around the world. At RISC-V Day Tokyo, the RISC-V community will share updates on new projects and implementations from its international membership, with a focus on current and prospective RISC-V projects and implementations that showcase the RISC-V ecosystem across Asia. RISC-V Foundation…

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Agenda For Inaugural RISC-V Summit in Santa Clara, Calif. from Dec. 3-6

Inaugural RISC-V Summit Agenda Dec. 3-6, 2018The RISC-V Foundation announced the agenda for its first annual RISC-V Summit at the Santa Clara Convention Center in Santa Clara, Calif. from Dec. 3-6, 2018. The Summit, in partnership with Informa’s Knowledge & Networking Division, KNect365, will gather the RISC-V ecosystem for a multi-track conference featuring keynotes, tutorials, exhibitions and networking receptions. The RISC-V Summit will host multi-track technical sessions, an exhibition hall and…

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RISC-V Foundation Announces Initial Keynote Speakers For Inaugural RISC-V Summit

The RISC-V Foundation, a nonprofit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced the keynotes for the first annual RISC-V Summit at the Santa Clara Convention Center in Santa Clara, Calif. from Dec. 3-6, 2018.The Summit, in partnership with Informa’s Knowledge & Networking Division, KNect365, will gather the RISC-V community for a multi-track conference featuring tutorials, exhibitions and…

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RISC-V Foundation Announces Call For Papers And Registration Promotions For Inaugural RISC-V Summit

Discounts on Conference and Exhibition Passes Available Now Through Sept. 17WHAT: RISC-V Summit in Santa Clara, Calif.WHERE: Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, Calif., 95054WHEN: Monday, Dec. 3 to Thursday, Dec. 6, 2018DETAILS: The RISC-V Foundation, in partnership with Informa’s Knowledge & Networking Division, KNect365, will hold its first annual RISC-V Summit at the Santa Clara Convention Center from Dec. 3-6, 2018. The Summit will be a major international…

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RISC-V Workshop in Chennai Proceedings

RISC-V Workshop in Chennai July 18-19, 2018 The RISC-V Workshop in Chennai, India took place July 18-19, 2018. Hosted by The Indian Institute of Technology Madras (IIT Madras) and sponsored by Western Digital, the RISC-V Workshop in Chennai discussed current and prospective RISC-V projects and implementations to influence the future evolution of the instruction set architecture (ISA) from Silicon Valley to Silicon Fenn and beyond.The event featured in-depth technical presentations…

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RISC-V Foundation Announces Agenda For RISC-V Workshop In Chennai

Workshop features more than 20 speaking sessions and a keynote from Western Digital WHAT: RISC-V Workshop in Chennai, IndiaWHERE: IC&SR Building, Indian Institute of Technology (IIT) Madras, Sardar Patel Road, Opposite to C, L.R.I, Adyar, Chennai, Tamil Nadu 600036, IndiaWHEN: Wednesday, July 18 and Thursday, July 19, 2018DETAILS: The RISC-V Workshop in Chennai will showcase the expansive RISC-V ecosystem, highlighting current and prospective projects and implementations that influence the future evolution…

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RISC-V Foundation at Design Automation Conference (DAC) Proceedings

RISC-V Foundation at Design Automation Conference (DAC) Proceedings June 24 – 27, 2018The 54th Design Automation Conference (DAC) was held at the Moscone Center West, in San Francisco from June 25 – 25, 2018. DAC 2018 demonstrated the exciting momentum of the RISC-V ecosystem. The RISC-V Foundation booth featured member companies Imperas Software, Microsemi, SiFive, Syntacore, UltraSoC and Western Digital. Throughout the event, the RISC-V Foundation hosted panels and speaking …

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