RISC-V at ESSCIRC-2014

We have presented our paper “A 45nm 1.3GHz 16.7 Double-Precision GFLOPS/W RISC-V Processor with Vector Accelerators” at the 40th European Solid-State Circuits Conference, which was held at Venice, Italy. This paper details our 45nm test chip, which has two 64-bit RISC-V Rocket scalar cores, each with a Hwacha vector accelerator attached to it. The paper and the talk will be available online shortly.

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RISC-V at HotChips-26

The RISC-V team was out in force at the HotChips-26 conference manning a sponsor booth.

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The Berkeley RISC-V team pose for a group shot at the end of the conference. From left to right: Steven Bailey, Henry Cook, Sagar Karandikar, Palmer Dabbelt, Krste Asanovic, Adam Izraelevitz, Colin Schmidt, Yunsup Lee, Andrew Waterman, Brian Zimmer, Scott Beamer, David Patterson.

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RISC-V Just Got a New Logo!

As we were getting ready for HotChips, we realized we were missing something very important: A logo!

Thanks to the creative designers at 99designs, we were able to get a pretty good logo in a week. The symbol visualizes RV, which we often use to abbreviate RISC-V when naming an ISA variant. The logo comes in two layouts. First, here’s the tall RISC-V logo:

riscv-symbol-text-standard-tall-square
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RISC-V GDB port

A RISC-V port of GDB is now available at https://github.com/mythdraenor/riscv-gdb.git courtesy of Todd Snyder at Bluespec, Inc., enabling source-level debugging of C/C++ codes compiled for RISC-V.  For any questions about this, please email support@bluespec.com.

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ISA Specification Version 2.0-1e-4 Now Available

After extensive rework based on feedback, we have finally released version 2.0-1e-4 of the user-level ISA spec. This is a major reworking of the ISA encoding, but we have updated all of our software tools to match. We anticipate this will be the final official version of the ISA, but welcome additional comments and feedback.

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