RISC-V in Verilog

V-scale, an implementation of an RV32IM core in Verilog has been released and is available at: https://github.com/ucb-bar/vscale.This core implements a simple, Z-scale-class pipeline, and is designed for integration with either existing microcontroller-class bus interconnects or the Rocket chip generator. The build infrastructure for both flows will be publicly released with an upcoming update to the platform of small RISC-V systems compatible with Z-scale.

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RISC-V at HotChips

Analyst Kevin Krewell has posted a HotChips preview at EE Times, which mentions the RISC-V Raven-3 presentation to be made in the last session at HotChips by Yunsup Lee.  UC Berkeley will again be sponsoring a table at HotChips to promote RISC-V, so please drop by if you’ll be there and want to chat about RISC-V uptake. 

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Save the Date for the 3rd RISC-V Workshop, Jan. 5-6, 2016

Please save the date and plan on joining us for the 3rd RISC-V workshop hosted courtesy of Oracle at the Oracle Conference Center in Redwood Shores, CA, January 5-6, 2016. This workshop will be the first event run by the newly formed RISC-V Foundation. The goals of the workshop are for the community to share information about recent activity in the various RISC-V projects underway around the globe, and to build consensus on future steps in the…

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2nd RISC-V Workshop Proceedings

June 29-30, 2015The International House, Berkeley, CA AboutThe goals of this workshop are for the community to share information about recent activity in the various RISC-V projects underway around the globe, and to build consensus on future steps in the RISC-V project, including the RISC-V foundation. This workshop features talks and poster presentations conveying recent activity in the RISC-V community at large, collected during an open submission period. Agenda Monday,…

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Open vs. Proprietary ISAs at CARD 2015

The fourth workshop on Computer Architecture Research Directions (CARD 2015), held in conjunction with the 42nd International Symposium on Computer Architecture, featured a mini-panel titled “Open vs. Proprietary ISAs” with David Patterson making the case for RISC-V.A video of the panel is now available online and can be viewed on YouTube.More about the panel, including the panelists’ position statements, can be found on the CARD 2015 website.

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Preliminary Agenda for the 2nd RISC-V Workshop is Posted!

The preliminary agenda for the 2nd RISC-V workshop is posted here. Thanks to the RISC-V community for submitting interesting talk proposals, we have a great program covering a broad range of exciting topics including: updates from many RISC-V projects around the globe; tiny RISC-V processors, out-of-order RISC-V processors, multi-core RISC-V processors, clockless RISC-V processors; 28nm RISC-V prototypes; verification; RISC-V privileged, compressed, vector extension proposals. We look forward to seeing you…

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RISC-V Draft Compressed ISA Version 1.7 Released

The RISC-V Compressed Instruction Set Manual Version 1.7 Draft proposal has been released and is available at this link. You can also download a PDF version at this link.We welcome community feedback and comments on this draft. In particular, we offer two options of what RVC should be. Thus, we need your feedback in order to decide which path to take. (The report lists the pros and cons of each…

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RISC-V Draft Privileged Architecture Version 1.7 Released

The RISC-V Privileged Architecture Draft Specification has been released and is available at: /specifications/privileged-isa/.This is only a proposal at this point, and we welcome community feedback and comments on this draft. Please participate in the discussion on the public sw-dev and hw-dev RISC-V mailing lists, to which you can subscribe on the www.riscv.org website. We hope to freeze the core parts of this privileged architecture specification later this year.We will very shortly be releasing an updated Spike…

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