Gizmochina Article: Huami Announces Huangshan No. 1, The World’s First AI-Powered Wearable Chipset

Today, at a launch event, along with Amazfit Verge Smartwatch and Amazfit Health Band 1S, Xiaomi-backed Huami also launched Huangshan No. 1 — the world’s first artificial intelligence powered wearable chipset.The Huangshan No. 1 (MHS001) is the world’s first wearable processor that comes integrated with AI neural network. It features four core artificial intelligence engines — cardiac biometrics engine, ECG, ECG Pro, and Hearth Rhythm Abnormality Monitoring Engine.It is also claimed to the…

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Wearable Article: Huami’s ‘First AI-Powered Wearable Chipset’ Takes Aim At Apple Watch

It’s been the month of wearable silicon – and off the back of the news of the Amazfit Verge, Huami announced that its developed the “world’s first AI-powered wearable chipset” – the Huangshan No. 1.For the uninitiated, Huami is a Chinese hardware company, pretty much backed by Xiaomi. It’s been turning out some pretty impressive devices, including the Amazfit Bip and Amazfit Stratos, both of which have mustered decent Wareable reviews.It’s using the RISC-V…

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Engadget Article: Huami’s New Watch And Bracelet Are Coming

Huami today updated its line of watches and bracelets. Among them, the new AMAZFIT smart watch has a similar appearance to the conventional sports watch. It is divided into three colors: black, white and blue. It also adopts a “soft, dry and stain-resistant” detachable silicone strap. It features a 1.3-inch round AMOLED screen (43mm dial) with a resolution of 360 x 360, a surface covered with Gorilla Glass 3 and a device…

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PULP Platform Announces HERO: Open Heterogeneous Research Platform

PULP Platform has released HERO, their Open Heterogeneous Research Platform, bringing PULP to the next level.HERO combines a PULP-based open-source parallel manycore accelerator implemented on FPGA with a hard ARM Cortex-A multicore host processor running full-stack Linux. HERO is the first heterogeneous system architecture that mixes a powerful ARM multicore host with a highly parallel and scalable manycore accelerator based on RISC-V cores. To read more, please visit: https://pulp-platform.org/hero.html.

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All About Circuits Article: RISC-V: All Hype Or Real Hope For The Processor Market?

Jothy Rosenberg, Founder and CEO of Dover Microsystems, a member of the RISC-V Foundation, contributes to All About Circuits discussing the impact of RISC-V and open source architecture on the semiconductor market.Created with the aim to revolutionize and democratize processor design for everything from mobile phones to industrial device controllers, RISC-V is changing the world of processor design. But what makes RISC-V so special? And is it all hype or…

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The Telegraph Article: Platform For Chip Designing

IIT Kharagpur is exploring the possibility of using a platform developed by a group of researchers at the University of California, Berkeley, that can be freely used for designing semiconductor chips.In the foreseeable future, Digital India will need application-specific chips in every conceivable domain but today only a handful of companies have the ability to design integrated circuits (IC).Inspired by the success of open source software, SiFive, a US-based company,…

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Wasiela Brings Encryption, FEC And Connectivity IP To DesignShare

SiFive, the leading provider of commercial RISC-V processor IP, today announced that Wasiela, a provider of innovative PHY-layer IP from the system and algorithmic levels all the way to implementation, has joined the DesignShare ecosystem. The availability of Wasiela encryption, forward error correction (FEC) and connectivity IP through the program will ease the development of reliable and secure high-throughput data communications for the RISC-V platform.Specific IP Wasiela plans to make…

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The Register Article: Arms Race: SiFive, Hex Five Build Code Safe Houses For RISC-V Chips

SiFive helps organizations turn semiconductor designs based on the open-source RISC-V instruction set architecture (ISA) into chips. On Monday, it announced it has integrated Hex Five Security‘s MultiZone Security trusted execution environment (TEE) into its Freedom SDK.The technical confection gives companies creating RISC-V chips the tools to implement a security environment comparable to ARM’s TrustZone, though perhaps without past flaws. It should help users of the SiFive toolchain bring security-enforcing silicon to market…

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Rambus Blog Post: No Need To Reinvent The Wheel: How Easy It Is To Build With RISC-V

RISC-V, an Open Instruction Set Architecture (ISA) designed with small, fast, and low-power real-world implementations in mind, has many advantages for OEMs. Alongside affordability, OEMs do not need to worry locking into a closed ecosystem.A decision on processing architecture is of huge importance and carries a significant cost. Once an OEM commits to a particular processor type (such as ARM, Qualcomm, or Intel) they commit considerable design resources, which often…

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Embecosm Blog Post: Supporting The RISC-V Vector Extension In GCC And LLVM

I recently attended the GNU Tools Cauldron in Manchester, where Roger Espasa from Esperanto Technologies and I ran a BoF session on GCC support for the RISC-V Vector (V) extension. This is an interesting topic, because the V extension has features that aren’t present in any other supported SIMD / Vector Architecture. This post is a short writeup of the current state of efforts towards supporting the extension in both GCC and LLVM,…

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