UltraSoC Blog Post: The RISC-V Ecosystem Has Many Layers

At our second Bristol RISC-V Meetup last Tuesday, a packed room of 70 delegates joined UltraSoC and Imperas Software, to discuss the latest updates on the RISC-V architecture and ecosystem.The engaging presentations at the Meetup covered a wide range of topics, including security, compliance, and code size optimization. UltraSoC CTO Gadge Panesar provided a ‘state-of-the-nation’ update from the RISC-V Foundation, as well as addressing some of the issues of systemic…

Read More...

All Electronics Article: Onespin Joins The RISC-V Foundation

The RISC-V Foundation has gained another member with OneSpin.Shortly before joining, the company has also introduced its RISC-V Integrity Verification Solution, thus supporting the dissemination of the RISC-V ISA. OneSpin enables the RISC-V community to develop and assess RISC-V cores based on a formal model of the RISC-V ISA instruction set implemented in the System Verilog (SVA).The OneSpin solution, embedded in a comprehensive verification framework, verifies compliance with the open…

Read More...

AB Open Article: Seeed Studio Opens Pre-Orders For RISC-V-Based Grove AI HAT Board

Seeed Studio has begun taking pre-orders for its Grove AI HAT for Edge Computing, an artificial intelligence-focused accelerator add-on for the Raspberry Pi which is based on the RISC-V Kendryte K210 processor.Based on the Sipeed MAIX M1 module, a development board for which the company crowdfunded late last year, the Grove AI HAT features a dual-core 64-bit RISC-V CPU running at 600MHz along with a 16-bit neural network co-processor dubbed…

Read More...

Phoronix Article: GDB 8.3 Debugger Brings RISC-V, Terminal Styling, C++ Injection, IPv6 Connections

The big GDB 8.3 feature release was just announced by Joel Brobecker. This update to the GNU Debugger comes with many improvements and new features for assisting developers.The GNU Debugger 8.3 release brings native configurations for RISC-V GNU/Linux and RISC-V FreeBSD, support for the C-SKY CPU architecture, OpenRISC GNU/Linux support, support for terminal styling on the CLI and TUI, experimental support for compilation/injection of C++ source code into the inferior,…

Read More...

PowerVR GPU And NNA Available On SiFive Platform

Imagination Technologies announced that it has joined SiFive‘s DesignShare ecosystem, giving system designers easy access to its industry-leading PowerVR GPU and neural network accelerator (NNA) IP cores. The PowerVR GPU will be the first fully featured GPU supporting the Vulkan® applications programming interface (API) available via the DesignShare ecosystem.DesignShare reduces the upfront costs of acquiring IP for System-on-Chip (SoC) prototyping. Imagination’s PowerVR Series8XE GPU and PowerVR Series3NX NNA IP will…

Read More...

Elektronik Article: RISC V Workshop At ETH Zurich

From June 11 to 13, the RISC-V Foundation organizes a RISC-V workshop in Zurich, at the ETH. It takes place in one of the most important RISC-V development centers.Open source hardware predicts professionals a bright future. The RISC-V Foundation even speaks of a development with disruptive potential. It is intended to fundamentally change the market for processor IP. Given the recent licensing disputes between Apple and Qualcomm, the idea of…

Read More...

Semiconductor Engineering Article: Week In Review: Design, Low Power

UltraSoC added cycle-accurate trace capabilities to its embedded monitoring and analytics infrastructure, initially as part of its processor trace solution for RISC-V. Targeting SSDs, servers, and real-time applications, the cycle-accurate tracing allows for optimization of hardware and software at the level of single clock cycles. To read more, please visit: https://semiengineering.com/week-in-review-design-low-power-42/.

Read More...

Wccftech Article: University Of Michigan May Have Developed First Unhackable Processor

The University of Michigan claims to have developed a completely unhackable processor, allowing data to be shuffled and encrypted faster than any hacking tools or programs, and much faster than a human could possibly decipher.The University of Michigan has developed a type of encryption accelerator know as Morpheus. Morpheus is a type of RISC-V processor designed with security as the highest priority. To read more, please visit: https://wccftech.com/university-of-michigan-developed-first-unhackable-processor/.

Read More...

LinuxGizmos.com Article: Latest Grove Add-On For The Pi Includes RISC-V NPU For Edge AI Duty

Seeed has launched a $24.50 “Grove AI HAT” with 6x Grove interfaces and Arduino IDE support for accelerating edge AI workloads on the Raspberry Pi. The HAT features a Sipeed MAix M1 module running a Kendryte K210 RISC-V neural processing chip. Neural acceleration chips seem to be everywhere these days — built into SoCs such as Qualcomm’s Snapdragon 845 or available in acceleration chips built on to add-on boards, such as Google’s…

Read More...

Geeky Gadgets Article: Raspberry Pi Grove AI HAT For Edge Computing $24

Internet of Things hardware enabler Seeed Studio has created a new Raspberry Pi Grove AI HAT specifically created for edge computing offering a low cost but powerful Raspberry Pi AI hat which assists the Raspberry Pi mini PC to run “AI at the edge”. But can also be used independently for edge computing applications if desired. The Grove AI HAT is built around the Sipeed MAix M1 AI MODULE and…

Read More...