EE Times Article: Rambus Taps RISC-V For Root Of Trust

Rambus announced a security block based on the RISC-V core aimed, in part, to plug the Meltdown/Spectre flaws revealed earlier this year. The CryptoManager Root of Trust targets use in a wide spectrum of ASICs, microcontrollers, and SoCs in embedded systems.Rambus claims that the new block sports several advantages over root-of-trust functions already integrated in most existing embedded processors. It suggested that OEMs should move this fundamental hardware-security function out of…

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Electronics Weekly Article: Rambus Launches CryptoManager RISC-V Core

Rambus is selling a programmable hardware security core built with a custom RISC-V CPU which it calls the CryptoManager Root of Trust.The secure processing core creates a siloed architecture that isolates and secures the execution of sensitive code, processes and algorithms from the primary processor. This mitigates the risk of critical vulnerabilities like Meltdown and Spectre and allows designers to optimize the primary processor for high performance, low power, or other characteristics while…

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Bit-Tech Article: Rambus Picks RISC-V For New Crypto Chip

Rambus has become the latest major industry name to take up the RISC-V open instruction set architecture (ISA), announcing the launch of a hardware security core designed for use in embedded platforms ranging from high-performance networking hardware to Internet of Things (IoT) products.Joining names including Nvidia and Western Digital, which has confirmed that it will be releasing a billion RISC-V cores in its storage products in the next two years, Rambus…

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Microsemi’s Mi-V Ecosystem Continues To Expand As New Member Antmicro Joins To Develop Mi-V RISC-V Processor Subsystems For PolarFire FPGAs

Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced Antmicro, an international research and development company known for its work with emerging technologies in embedded and cyber-physical systems, has joined Microsemi’s Mi-V™ RISC-V ecosystem. As the maker of the open source Renode framework for multi-node simulation, Antmicro has implemented support for Microsemi’s Mi-V, RISC-V-based soft central processing units (CPUs) and the solution’s integration with Microsemi’s SoftConsole software…

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RISC-V Foundation Announces Agenda For Workshop In Barcelona

Workshop features more than 30 tutorials, presentations, networking receptions and a tour of the Barcelona Supercomputing CenterWHAT: RISC-V Workshop in Barcelona, Spain WHERE: Universitat Politècnica de Catalunya, Campus Nord, Calle Jordi Girona, 1-3, 08034 Barcelona, SpainWHEN: Monday, May 7 to Wednesday, May 9, 2018DETAILS: Co-hosted by the Barcelona Supercomputing Center and the Universitat Politècnica de Catalunya (UPC), the RISC-V Workshop in Barcelona gathers the RISC-V ecosystem to share notable RISC-V…

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Rambus Launches CryptoManager RISC-V Root Of Trust Programmable Secure Processing Core

Rambus Inc. (NASDAQ: RMBS) today announced the availability of the CryptoManager Root of Trust, a fully programmable hardware security core built with a custom RISC-V CPU. The secure processing core creates a siloed architecture that isolates and secures the execution of sensitive code, processes and algorithms from the primary processor. This mitigates the risk of critical vulnerabilities like the recent Meltdown and Spectre security flaws and allows designers to optimize the primary processor for…

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Dover Microsystems Brings Secure Silicon IP to SiFive’s DesignShare

SiFive, the leading provider of commercial RISC-V processor IP, today announced that Dover Microsystems, a cybersecurity solutions provider, is the latest vendor to join the DesignShare ecosystem.Dover Microsystems will make available its CoreGuard Silicon IP, which comprises hardware technology that enables processors to defend themselves in real-time from all network-based attacks. With CoreGuard, system designers have assurance that their SiFive-based host processor is protected at the instruction level. CoreGuard prevents…

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WIRED Article: Using Open Source Designs To Create more Specialized

The open source movement changed how companies build software. Facebook, Twitter, and Yahoo employees pitched in during the early days of the data-crunching software Hadoop. Even after the relationship between Apple and Google soured, the companies’ coders kept working together on an obscure but important piece of software called LLVM. Microsoft now uses and contributes to the Linux operating system, even though it competes with Windows.The embrace of open source isn’t…

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Codasip Welcomes Jerry Ardizzone To Executive Team As Vice President Of Worldwide Sales

Codasip, the leading supplier of RISC-V embedded processor intellectual property, today announced that Jerry Ardizzone has joined as Vice President of Worldwide Sales, reporting to CEO Karel Masařík.“We are very excited to have Jerry on board to lead our global sales efforts,” declared Karel Masařík, CEO and founder of Codasip. “As RISC-V momentum grows, Codasip’s reach is expanding worldwide, and we need the leadership and international expertise that Jerry has…

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SatMagazine Article: Improving Space Systems Designs Using FPGAs With RISC-V Cores—A Microsemi Tech Focus

Designers face many unique challenges when developing systems used in space that do not exist for terrestrial systems. Among these are the need to ensure the trustworthiness of intellectual property (IP), overcome a lack of widespread industry support for radiation-tolerant devices, and amortize high design costs across low production volumes.These challenges are particularly important when evaluating processors for space designs, and difficult to solve using a closed processor architecture. That…

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