ElectronicsWeekly Article: Raspberry Pi HAT Brings RISC-V, AI, Edge Computing

An add-on to Raspberry Pi delivering AI-at-the-Edge development capability, can be pre-ordered now for $24.50 or bought for $28.90 when it becomes generally available on June 15th.The RISC-V based Grove AI HAT, from Seeed Studio, brings an AI capability to Raspberry Pi  allowing it to be used to develop AI using neural nets.The Grove AI HAT is a $25 add-on connecting through Pi’s GPIO pins. It contains a Sipeed MAIX M1 AI Module, which…

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ElectronicsWeekly Article: UltraSoC Adds Cycle-Accurate Trace To Analytics Capability

UltraSoC has added cycle-accurate trace technology to its embedded monitoring and analytics capability that allows designers of high-performance computing, storage and real-time devices to see not only what is happening inside devices, but critically, when something occurred.Cycle-accurate tracing is increasingly important in real-time and performance-critical applications, where engineers need to optimize the operation of their hardware and software code down to the level of single clock cycles – the smallest…

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Elektronik Praxis Article: RISC-V Foundation Continues To Grow: OneSpin Introduces Key Integrity Checking Tool

The RISC-V-Foundation continues to grow: the latest member is the Munich-based company OneSpin Solutions. OneSpin is a provider of certified IC Integrity Verification solutions and has introduced its “RISC-V Integrity Verification Solution” before joining. This solution enables the RISC-V community to develop and test RISC-V cores based on a formal model of the RISC-V-ISA implemented in SystemVerilog (SVA).The solution, which is provided as a series of formal applications and integrated…

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TechRepublic Article: $25 Raspberry Pi Add-On Gets You Started With Edge Computing AI

Seeed Studio is bringing RISC-V capabilities to the Raspberry Pi with the Grove AI HAT for Edge Computing, a $25 add-on to the Raspberry Pi—sitting on top, connecting using the RPi’s GPIO connector pins—equipped with a Sipeed MAIX M1 AI Module, which utilizes a Kendryte K210 processor.The Grove AI HAT includes six Grove interfaces, including one each for Digital I/O, PWM, I2C, and UART, and two ADC, as well as…

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Leiphone Article: What Is One Of The Keys To The Rapid Introduction Of RISC-V Processors In Western Digital?

The RISC-V instruction set officially released the first edition of the user manual in 2014. Since then, NVIDIA, Western Digital, Qualcomm, HiSilicon, Alibaba, Samsung and other world-renowned companies have joined the RISC-V Foundation and promoted the development of the RISC-V ISA. However, RISC-V wants to be as successful as x86 and Arm, and the construction of the ecosystem is critical for companies like Western Digital and HiSilicon to launch the…

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Embedded Computing Design Podcast: Five Minutes With…Calista Redmond, CEO, RISC-V

RISC-V is the new instruction-set architecture that people can use to design microprocessors. Calista Redmond is the newly appointed CEO of the RISC-V Foundation, the group that manages the spec and is putting on seminars and conferences around the world. In this week’s Five Minutes With…discussion, I asked Calista about her plans for the organization, which potentially plays a large role in our industry moving forward. To read more and listen…

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Media Alert: SiFive Tech Symposiums On RISC-V Coming To Europe This Month

WHO: SiFive, the company founded by the inventors of the RISC-V architecture, and leading provider of commercial RISC-V processor IP and custom SoC solutions, and several co-hosts and ecosystem partners, including: Co-hosts: Imagination Technologies, Mentor, Qamcom, Syntacore Partners: Antmicro, Credo, IAR Systems, Rambus, SecureRF, UltraSoC WHAT: The SiFive Tech Symposiums on RISC-V will take place in six cities in Europe throughout the month of May. These highly educational events are free to attend, and present many…

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Michigan News Article: Unhackable: New Chip Stops Attacks Before They Start

A new computer processor architecture developed at the University of Michigan could usher in a future where computers proactively defend against threats, rendering the current electronic security model of bugs and patches obsolete.Called MORPHEUS, the chip blocks potential attacks by encrypting and randomly reshuffling key bits of its own code and data 20 times per second—infinitely faster than a human hacker can work and thousands of times faster than even…

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Embarcados Webinar: An Introduction To RISC-V ISA And Its Ecosystem

An introductory webinar on RISC-V will be held on May 15th on the “Embarcados portal”, one of the largest Brazilian community-based websites for embedded systems, IoT, edge computing, etc. This type of webinar from Embarcados typically receives a large amount of viewership from all over Brazil. This introductory webinar will support the spread of awareness and use of RISC-V in communities around Brazil. To read more and register for the webinar,…

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EDN China Article: Why Is Cycle-Accurate Tracking Important In SoC Design?

UltraSoC today announced a new technology, Cycle Precision Tracking, for embedded monitoring and analysis infrastructure. By adding cycle-accurate tracking capabilities, real-time application developers leveraging UltraSoC embedded analytics can not only see what’s happening inside the device, but more critically, see when something happens.Cycle-accurate tracking technology will initially be available as part of UltraSoC’s RISC-V processor tracking solution, a rapidly growing open source processor project.Each storage product in Western Digital includes…

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