The 2020 Design Automation Conference Unveils Keynotes and SKYtalk Speakers

LOUISVILLE, Colo.–(BUSINESS WIRE)–The Design Automation Conference (DAC) returns for its 57th year with an incredible lineup of keynotes and SKYtalks. Founded in 1964, DAC is the longest running and largest event focused on research and technology for the design and automation of electronic circuits and systems. More than 6,000 attendees from academia, research, government, and industry attend the live conference. With DAC 2020 being virtual, conference attendees from all over the globe will…

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RISC-V Crypto Core Is Qualified To Asil-D For Automotive Designs | Nick Flaherty, EENews Europe

Rambus has received ASIL-D qualification for its CryptoManager Root of Trust co-processor crypto core.The RT-645 crypto core, based around a custom RISC-V processor, has been certified as ASIL-D ready by SGS-TÜV Saar. The automotive-grade secure co-processor IP safeguards SoCs in V2X communications, ADAS, ECU platform management, infotainment and other critical vehicle systems.Article: https://www.eenewseurope.com/news/risc-v-crypto-core-qualified-asil-d-automotive-designs

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Making FPGA SoC Easier | Kevin Morris, EE Journal

There are about a zillion SoCs on the market today, perhaps even a zillion and a half, we haven’t counted in awhile. Of course most of them are built on various forms of ARM MCUs or applications processors, and the line card includes a zillion squared permutations with various collections of peripherals and interfaces parked alongside the processor. It can be a dizzying experience to design a system around one,…

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New Series: OpenHW TV – Open Source IP Verification

This first episode of OpenHW TV is focused on the Verification of CORE-V open source RISC-V processor IP cores. Guests include the new Co-Chairs of the OpenHW verification task group (Futurewei and SiliconLabs) with contributing members Imperas and Metrics highlighting the open source CORE-V processor IP Design Verification (DV) plan using state of the art flows and SystemVerilog UVM test-benches with encapsulated Imperas RISC-V reference model, coverage based flow, and Metrics flexible cloud based environment. Following the updates and presentations by Imperas…

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A guide to accelerating applications with just-right RISC-V custom instructions | Lee Moore, Duncan Graham, Embedded Magazine

The open instruction set architecture (ISA) of RISC-V permits broad flexibility in implementation and offers optional features that can enable fresh approaches to resolving hardware-software design tradeoffs. Based on a modular structure, a number of standard extensions and options can be used to configure the base processor as a starting point. Yet the true value actually lies in the opportunities that RISC-V offers developers to create new extensions, instructions and…

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Simon Davidmann on Axiomise podcast

In this week’s episode, Ashish Darbari talks to Simon Davidmann – Founder & CEO of Imperas Software Ltd. Simon talks about his journey from being an inquisitive child to becoming the CEO of Imperas. His many influences on our industry include Verilog, SystemVerilog, and the fascinating work being done at Imperas in creating simulators for multiple different processor families, including Arm, RISC-V International, and MIPS.Podcast at: https://www.linkedin.com/feed/update/urn:li:activity:6676097173899268096/

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