Sohu Article: RISC-V Ecological Status And Development Examples

On January 4 this year, the Zhishang Open Class officially launched the RISC-V series, focusing on the Chinese RISC-V ecosystem. In the past year, the open instruction set architecture has received a significant amount of attention, and many semiconductor companies in China have announced their participation in the RISC-V camp. The RISC-V ecosystem is still in its early stages of development. Especially in China, there are very few companies that actually launch…

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Hackster.io Article: Raspberry Pi Becomes A Member Of The RISC-V Foundation

Earlier today we had a bit of a surprise with the news that Raspberry Pi has joined the RISC-V Foundation as a member.The RISC-V Foundation has a tiered membership structure, with the Silver membership level giving the participating organization one vote per open position on the Foundation’s board, and allowing them to participate in the Foundation task groups and contribute to the upkeep of the RISC-V ISA. To read more, please visit: https://blog.hackster.io/raspberry-pi-becomes-a-member-of-the-risc-v-foundation-11f06aecc241.

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CCIDnet.com Article: Top Ten News Events Of China’s Semiconductor Industry In 2018

In 2018, RISC-V received extensive attention from academic communities and recognition from a variety of industries. A number of RISC-V-based innovative forces emerged including Hangzhou Zhongtianwei, Beijing Junzheng, Huami Technology and Corelai Technology. Local governments also support RISC-V related design and development companies.Comments: The development of independent intellectual property rights and mastering core technologies has become the consensus of China’s integrated circuit industry. To read more, please visit: http://www.ccidnet.com/2019/0104/10448947.shtml. Please note that the…

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EET Asia Article: Riding The IoT Wave With Wi-Fi HaLow

After an unusual two-year delay, silicon for a new Wi-Fi standard is starting to emerge. Over the next few months, a handful of startups will sample chips for 802.11ah, a 900-MHz version of Wi-Fi targeting long-range links especially for the internet of things. The so-called HaLow products promise delivery of up to Mbits/s over distances of tens of meters to a kilometer and support for thousands of nodes on an…

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Phoronix Article: More Details On The Proposed Simple-V Extension To RISC-V For GPU Workloads

With the proposed Libre RISC-V Vulkan accelerator aiming to effectively be an open-source GPU built atop the open-source RISC-V ISA there were recently some new details published on how the design is expected to work out.For this very ambitious libre RISC-V SoC design. that EOMA68 developer Luke Kenneth Casson Leighton wants to pursue through crowdfunding, it’s just not a matter of spinning his own RISC-V design but for making the SoC suitable for…

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EET India Article: Krste Asanović : RISC-V Momentum Is Massive In India

When Krste Asanović, chief architect and leader of the team at UC Berkeley that defined the open RISC-V ISA recently visited India for the first time, he was absolutely confident that he would come again.Not just because he loves Indian food which he had fallen in love with during his childhood in England but because there has always been a long-standing and strong Indian connection with IIT Madras which has…

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OpenSystems Media Newsletter: IoT Design Weekly – 01.03.2018

Linux, RISC-V Foundations to Collaborate on Open Architectures: The Linux Foundation and RISC-V Foundation have announced a joint collaboration agreement to accelerate the development and adoption of the RISC-V ISA using Linux tools infrastructure, services, and training programs. To read more, please visit: http://my.opensystemsmedia.com/index.php/email/emailWebview?mkt_tok=eyJpIjoiWWpFMFlXRXhZVFl4Wm1KbCIsInQiOiJpdXMxeFVkblZ2RjVWK1JRdU40UWd3NU50cHFsMUdKb1llanExUUo5MlRNblJTanY0dWUxblVRQmNoRnhwV05QaWJhZXhcL1RvMDRvQnFzU256NGV4S1V3NGkrWjV5UGptRkJuME1DQ3pBRTQ0d1RKVitUdFl2aCtwQnA1c3JPNG0ifQ%3D%3D.

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Forbes Article: Digital Storage Projections For 2019, Part 2

This is the second in our three-part 2019 digital storage projection blog series. This part looks at 2018 trends and future developments in solid state storage, memory and fundamental computer architectures. In particular we will look for developments in fast storage interfaces, in particular NVMe and fabrics built with NVMe (NVMe-oF). This piece will also look at trends in emerging non-volatile memories and their use in new computing architectures such…

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Electronic Specifier Article: Optimizing Performance In High-Performance AI Chip

Provider of complete In-Chip PVT Monitoring Subsystems, Moortec Semiconductor, has announced that Esperanto Technologies have selected its complete 7nm Embedded In-Chip Monitoring Subsystem IP for Process, Voltage and Temperature Sensing to optimise performance and increase reliability for their AI Supercomputer-on-a-Chip. Esperanto develops high-performance, energy-efficient computing solutions for Artificial Intelligence (AI) and machine learning (ML) applications based on the open standard RISC-V ISA (Instruction Set Architecture).As a founding member of the…

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Andes Technology Video: The Promises And Pitfalls Of RISC-V, From SoC Design Perspective (D&R IP SoC Day Panel)

On Thursday, April 5, 2018, Design&Reuse hosted the D&R IP SoC day at the Hyatt Hotel Santa Clara. Presenting at panel, “The Promises And Pitfalls Of RISC-V, From SoC Design Perspective,” Emerson Hsiao of Andes Technology USA Corp. joins Art Swift of Esperanto Technologies, Inc., Ted Speers of Microsemi Corp. and Naveed Sherwani, SiFive, Inc. to discuss the advantages and disadvantages of RISC-V for chip design. To read more, please visit: https://www.youtube.com/watch?v=68y_WoqP6LY.   

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