CNbeta Article: How Can China Find A Breakthrough In The Field Of Open Source Chips? RISC-V Will Be A Great Opportunity

Dr. Fang Zhixi, the chairman of the China Committee of the RISC-V Foundation and former vice president of Intel, talks about the emergence of RISC-V and how it has revolutionized the field of microprocessors. As an open source hardware instruction set architecture, RISC-V, born in UC Berkeley since 2010, is characterized by its simplicity, stability, complete open source and free of charge, while separating the reference and extension instructions. Customized modules…

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Golem.de Article: RISC-V Base Frozen And Ratified

Although the specification of the free RISC-V instruction set has been available for years and some different CPU implementations already exist, the RISC-V consortium has only now officially ratified the specification. This software was built to this specification and works forever on RISC-V processors. To read more, please visit https://www.golem.de/news/cpu-befehlssatz-risc-v-basis-eingefroren-und-ratifiziert-1907-142503.html. Please note that the original article is in German.

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Developpez Article: RISC-V Foundation Announces Ratification Of RISC-V Core ISA Specifications

RISC-V comes with a new set of instructions that promises scalability from microcontrollers to supercomputers and offers user-defined scalability, allowing companies to differentiate themselves with custom instructions.  The RISC-V Foundation  today announced the ratification of the RISC-V base ISA and privileged architecture specifications. The RISC-V base architecture is the interface between application software and hardware. Software that’s coded to this specification will continue to work on RISC-V processors in perpetuity,…

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IT BitNews Article: Core System Validation ‘No Problem’ … “Enhanced Ecosystem, Increasing Utilization Of RISC-V Core”

Through the development of information and communication technology (ICT) and the establishment of next-generation network infrastructure, it is expected that attention for connectivity between objects will accelerate rapidly.Changes are also being detected in the embedded system market. With the growth of the IoT market, the RISC-V ISA, which can be designed as a customized core, is becoming more popular. The RISC-V Foundation offers a open-source RISC open instruction set for everyone…

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Fabcross Article: Switch Science Launches M5Stack AI Camera And Sipeed AI Development Board

Switch Science Inc. announced that the M5 Stack AI camera “M5 Stickk” and the Sipeed AI development board “Sipeed Maix” series on July 5, 2019. The M5 Stickk is equipped with a Kendryte K210 RISC-V dual-core processor, a high-performance neural network processor (KPU) and dual-core 64-bit RISC-V CPU enable low-cost, providing high-energy efficient and high-performance image processing.  To read more, please visit https://fabcross.jp/news/2019/20190710_switchscience_m5stackaicamera_sipeedaidevboard.html. Please note that the original article is in Japanese.

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IT Home Article: The RISC-V ISA Explained

A few days ago, Xiaozaojun introduced the open source base station O-RAN and discussed the semiconductor industry as well as the RISC-V ISA that many people call “open source architecture.”Under the combined effect of internal and external factors, the state has strengthened its investment in the chip field, and more and more enterprises have begun to attach importance to investment in chip research and development. And RISC-V, at this critical…

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All About Circuits Article: CHIPS Alliance Brings Powerful Players Into Open Source Hardware Collaboration

Linux changed the world with its open approach to operating systems. The Linux Foundation has now partnered with a new initiative, CHIPS Alliance, to bring the same open source ethos to hardware design. All About Circuits had a chance to speak to Ted Marena, Interim Director of CHIPS Alliance, about CHIPS Alliance, its mission, and its inaugural event this June, which was hosted by Linux, itself. Linux changed the world with its…

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Phoronix Article: LLVM’s RISC-V Compiler Back-End Looks To Go Official For 9.0 Release

The RISC-V compiler back-end currently within the LLVM tree has been treated as “experimental” but for the in-development 9.0 release, it could become an “official” back-end. Thanks to good unit test coverage, a 100% pass rate on the GCC torture suite, and other good test coverage, there is an effort now to make this RISC-V target official for LLVM. To read more, please visit: https://www.phoronix.com/scan.php?page=news_item&px=LLVM-9.0-RISC-V-Official-Aim.

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All About Circuits Article: Open Memory-Centric Architectures Enabled By RISC-V And OmniXtend

OmniXtend is a cache coherence protocol that encapsulates coherence traffic in Ethernet frames and can be used to scale memory-centric applications. Today’s data centers are struggling to keep up with the explosive bandwidth requirements of big data. In many applications, such as artificial intelligence, bioinformatics, and in-memory databases, we commonly run into practical limitations dictated by the maximum available size of main memory. Because this memory is controlled by the…

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36Kr Article: Is India Semiconductors Rising?

India’s actions in the semiconductor field have been small in recent years. First, India has established RISC-V as the national instruction set. In this dynamic, the SHAKTI project team responsible for RISC-V development has adjusted its goal to develop six open source processor cores based on the RISC-V instruction set, covering 32-bit single-core microcontrollers, 64-core 64-bit high-performance. Multiple application areas such as processors and security processors. To read more, please visit https://36kr.com/p/5222715. Please note…

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