EETimes Article: 8 Top Innovations Of 2017

A few crack grad students and professors at Berkeley have done a lot in the past few years to spawn a new microprocessor architecture unencumbered by royalties. Their efforts also sparked new possibilities for open source hardware. Even the veteran co-founders of this movement are amazed this could happen given the consolidation and maturity of today’s semiconductor industry. This is arguably an award that could be held until next year given…

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Fuse Article: Esperanto Exits Stealth Mode, Aims At AI With A 4,096-core 7nm RISC-V Monster

You have probably never heard about Esperanto before and there’s a good reason for that. The startup has been cloaked in secrecy, at least until recently that is. At the 7th RISC-V Workshop Esperanto finally gave us some glimpse into what they were up to. Esperanto Technologies was founded in 2014 and have pretty significant backing from companies such as Western Digital. Esperanto president and CEO is none other than…

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Sensors Online Article: Extendable Platform Kit Drives FPGA-Based RISC-V Designs

Microsemi and Imperas Software Ltd. launch the Extendable Platform Kit for Microsemi Mi-V RISC-V soft central processing units (CPUs). The collaboration delivers the first commercially available instruction set simulator (ISS) for Microsemi’s Mi-V ecosystem, a program designed to increase adoption of Microsemi’s RISC-V soft CPU product family utilizing RISC-V open instruction set architectures (ISAs).To read more, please visit: https://www.sensorsmag.com/components/extendable-platform-kit-drives-fpga-based-risc-v-designs

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AnandTech Article: Western Digital To Use RISC-V For Controllers, Processors, Purpose-Built Platforms

Western Digital recently announced plans to use the RISC-V ISA across its existing product stack as well as for future products that will combine processing and storage. The company plans to develop RISC-V cores internally and license them from third parties to use in its own controllers and SoCs, along with using third-party RISC-V based controllers. To develop the RISC-V ecosystem, Western Digital has already engaged in partnerships and investments…

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EE Journal Article: Visualizing Real-Time Issues Swedish Company Gives Developers Better Insight

I had planned this piece some months ago, but suddenly it has become tied into a major breaking news story. In the last ten or so years, the RTOS (Real-Time Operating System) has moved from being a relatively rare beast to becoming almost commonplace, as applications, particularly those built as embedded systems, have demanded communication and, particularly in the Internet of Things (IoT), have added sensing. To manage the complexities…

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eeNews Europe Article: Extendable Platform Kit To Ease Adoption Of FPGA-Based RISC-V Designs

Microsemi Corporation and Imperas Software partnered on the development of what they believe to be the first commercially available instruction set simulator (ISS) for Microsemi’s Mi-V ecosystem, the Extendable Platform Kit for Microsemi Mi-V RISC-V soft central processing units (CPUs). The program is designed to boost the adoption of Microsemi’s RISC-V soft CPU product family utilizing RISC-V open instruction set architectures (ISAs). Imperas’ Virtual Extendable Platform Kit provides a software…

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Electronics Weekly Article: Microsemi And Imperas Develop RISC-V ISS

The collaboration delivers the first commercially available instruction set simulator (ISS) for Microsemi’s Mi-V ecosystem, a program designed to increase adoption of Microsemi’s RISC-V soft CPU product family utilizing RISC-V open instruction set architectures (ISAs). “The Imperas EPK allows for rapid software development and debugging of corner cases when using Mi-V soft CPUs on Microsemi field programmable gate array (FPGA) products. We look forward to working with Imperas and other Mi-V ecosystem…

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Embedded Computing Design Podcast: Five Minutes With…Jack Kang, VP Of Product And Business Development, SiFive

RISC-V has caused a slew of start-ups. One of those, SiFive, is composed of some of the folks behind the original spec, derived at Berkeley. Jack Kang, SiFive’s Vice President of Product and Business Development, had a great perspective on the RISC-V instruction set architecture, and cleared up some of the misconceptions. On this week’s Five Minutes with…interview, Jack went through everything from the latest silicon announcements to the all-important…

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Embedded Computing Design Article: Inflection Point For RISC-V: The 7th RISC-V Workshop In Silicon Valley

The 7th RISC-V Workshop was held in Silicon Valley last week, hosted by RISC-V Foundation founding member Western Digital (WD). Each workshop has a different feel to it, and this one seems to be the inflection point in RISC-V maturity. Whereas past workshops felt a bit like a revival tent meeting, with most everyone caught up in the religion of RISC-V, at this workshop there was also a strong sense of…

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