RISC-V Learn Online provides online learning at beginner, intermediate, and advanced levels. Designed to increase engineering expertise and career opportunities on RISC-V across the industry and directly benefiting the community, get ready to start your learning journey!
Check out our new courses!
Learn all about RISC-V: find out how to work with open specifications and the organization that curates them, and discover how you can become a part of this vibrant community.
This course is divided into five chapters:
- Chapter 1: Getting to Know RISC-V, which introduces RISC-V as a technology, an organization, and a community to give you a better understanding of what RISC-V is.
- Chapter 2: The RISC-V Story, which goes into great detail about the history of RISC-V, RISC-V International, the organization of RISC-V governance, working groups and committees, and how all of these people communicate effectively together.
- Chapter 3: The RISC-V Community, which outlines the processes by which the RISC-V community manages, extends, and improves all of the artifacts within RISC-V – the ISA and other specifications, working policies, development practices, and more.
- Chapter 4: Developing RISC-V, which uses all of the prior information to describe the hard details about collaboratively developing the specifications, software, compliance tests, and other related artifacts.
- Chapter 5: RISC-V in Practice, the hands-on chapter where you will see the RISC-V ISA in action through the use of the QEMU emulator/virtualizer, creating a processor using SystemVerilog, and running an operating system on actual hardware.
We expect that by the end of this course, you will have a solid grounding in all of the activities related to RISC-V. You will learn how to read and understand the specifications, and understand the processes involved in curating and extending them. You will understand how to work effectively with RISC-V International and the RISC-V community. And you will understand where to go for additional information.
Create a RISC-V CPU with modern open source circuit design tools, methodologies, and microarchitecture, all from your browser.
This mini-workshop is a crash course in digital logic design and basic CPU microarchitecture. Using the Makerchip online integrated development environment (IDE), you will implement everything from logic gates to a simple, but complete, RISC-V CPU core. You will be amazed by what you can do using freely-available online tools for open-source development. You will walk away with fundamental skills for a career in logic design, and you will position yourself on the forefront by learning to use the emerging Transaction-Level Verilog language extension (even if you don’t already know Verilog).
RVFPGA: The Complete Course in Understanding Computer ArchitectureBuilding a RISC-V CPU Core (LFD111x)
The RVfpga under-graduate course provides the foundation knowledge and hands-on experience that the next generation of Programmers and Engineers need to harness the potential of RISC-V. It is structured for Teachers to use with their Students, but can also be used for self-study. Supporting videos, workshops and online courses are in development.
We follow the essential principle ‘by academics for academics’ in the creation of all teaching materials. RVfpga is a collaborative effort between Imagination Technologies’ University Programme (“IUP”), UNLV – University of Nevada Las Vegas and UCM – University Complutense University of Madrid. Our curriculum guides and reviewers are from UCB – University of California, Berkeley and PDX – Portland State University.
The RVfpga package provides instructions, tools, and labs that show how to:
- Target a commercial RISC-V system to an FPGA
- Add more functionality to the RISC-V system
- Analyse and modify the RISC-V core and memory hierarchy
It will consist of 20 Labs in total with detailed instructions, examples, short questions and practical exercises with solutions, giving teachers flexibility to choose between a practical and an exam-based structure for the course.
- The Getting Started Guide, and Labs 1 to 10, is available now, in English (released Nov’20). Chinese (Traditional & Simplified) March ’21.
- Labs 11 to 20 are due Nov’21
- “RVfpga: An Introduction to SoC Design” – this is an MSc course that takes the core and builds it an SoC running an RTOS. Due May ‘21
The RVfpga system uses Chips Alliance’s SweRVolf SoC, based on Western Digital’s RISC-V SweRV EH1 core. The SweRV is a fully-verified production level processor core. It is fully open-source, and now being used in silicon by several companies. Imagination Technologies use it in their latest GPUs (A and B series).
Course link (Imagination) https://
- RISC-V (RV32I) Processor Architecture and Applications
- Guided self-paced lessons, with processor control, sandboxes and knowledge checks
- Using remote hardware (live feed of Xilinx PYNQ FPGA module towers on right).
- Demos of RISC-V processor hardware operation for each instruction
- Online RISC-V assembly program simulation (Venus)
- remote RISC-V hardware program upload and execution (with hardware debug)
- Capture and simulation of RV32I hardware description language model using Xilinx Vivado EDA tools
- Develop game applications using RISC-V assembly programming
- Pipelined processor operation, hazard detection and handling
- Introduction to C programming for RISC-V
- RISC-V (RV32I) Processor Architecture and Applications
viciLogic online training courses interact with remote FPGA hardware, controlling and observing digital logic signal behaviour in real time. Your browser controls remote hardware input signals in course steps, probes internal signal state, presents interactive course diagrams with dynamic overlayed signal widgets.
Maven Silicon offers five on-demand online courses by Sivakumar P R.
- RISC-V Instruction Set Architecture: This RISC-V ISA course explains RISC-V Instruction Set Architecture and all RV 32 I Instructions in detail with various examples.
- RISC-V R32I RTL Design: This RISC-V RTL Design course explains the complete RTL design process, how you can create a basic architecture for J-type instructions initially and scale up the same sequentially in phases to implement all other RV 32 I instructions.
- RISC-V ISA & RV32I RTL Architecture Design: This RISC-V training course trains you extensively on the RTL design using Digital Electronics which includes the concepts of combinational, sequential, FSM logic designs and Memories.
- RISC-V RV32I RTL Design using Verilog HDL: This RISC-V hands-on training course explains the RISC-V ISA, pipeline RISC-V processor RTL design architecture and how to implement the RTL design using Verilog HDL.
- RISC-V RV32I RTL Verification using UVM: This RISC-V hands-on training course explains the RISC-V ISA, pipeline RISC-V processor RTL design architecture and how to verify the RISC-V Verilog RTL design using UVM.
VSD-RISCV: Instruction Set Architecture (ISA), via Udemy
Part 1a: This course will talk a lot about RISC-V ISA from scratch, also including a section about why do we even need a computer architecture and how real-time day-to-day apps run on a computer, with examples
The final aim of this course is to help everyone to build a robust specifications, which is the very first criteria behind system design. In the upcoming courses,, these specifications will be coded in RTL hardware description language using verilog/vhdl and finally the RTL will placed and routed using opensource EDA tool chain.
This course will walk you through the specifications, starting from signed/unsigned integer representation till RV64IMFD Instruction set with some really cool images and examples. The conventions like “IMFD” will also be explored in a unique fashion, which is being never done before and any micro-processor or micro-controller related courses
Part 1b: This course is in continuation with my previous course, which dealt with RV64I integer instructions. We also looked at a sample program coded in RISC-V assembly language and viewed the contents of all 32 registers present in RISC-V architecture.
All concepts viewed in Part 1a form the basis of this course and viewer is expected to cover Part 1a course at least 70%. This course deals with some advanced topics of multiply extension (RV64M) and floating point extension (RV64FD) of the RISC-V architecture – An important one needed in today’s fast changing computing world.
We also have explored some facts about hardware, which is the basis of next course (to be launched soon) where we will code the RISC-V ISA using verilog.