lowRISC, Future ship its first RISC-V FPGA dev board, Esperanto announce its 4,112-core RISC-V AI accelerator, SiFive announce and release the HiFive Unleashed alongside its E7, S7, and U7 RISC-V core families, GreenWaves launch the GAP8 application processor, Fedora release RISC-V disk images, the PULP Platform release PULPissimo, Ariane, and HERO cores, Debian Linux ported to RISC-V, Lime Micro and SiFive announce work on a RISC-V LimeNET base station, the world’s first fully photolithographic homebrew IC, OnChip announce its Itsy-Chipsy fabrication platform and 32-bit RISC-V microcontroller, Rambus’ CryptoManager core, SeL4 for RISC-V, significant progress in OpenPiton project, the SHAKTI project boot outsourced and native RISC-V parts, Zephyr for RISC-V, Mobiveil’s RISC-V programmable storage and Fadu’s SSD controller, Bluespec’s Piccolo and Flute RISC-V cores, the clever Retro-uC, an “overnight” RISC-V implementation, Western Digital’s continued support and evangelism culminating in its SweRV RISC-V core, Buildroot support, desktop Fedora for RISC-V, a RISC-V Soft CPU competition, Eideticom’s P2PDMA support patches, low-cost RISC-V development boards, multi-zone security, the OpenPiton+Ariane collaboration, a free RISC-V VEGAboard for US developers, Microsemi’s PolarFire SoC, a partnership between the RISC-V Foundation and Linux Foundation, Thales’ support for RISC-V and partnership with IIT Madras, the JuxtaPiton project, funding for open-source transprecision computing projects, the surprise announcement that the Raspberry Pi Foundation is to support RISC-V, Wave Computing’s MIPS Open intiative, and a panicked Arm launch, then cancel, an aggressive anti-FOSSi marketing campaign. To read more, please visit: https://abopen.com/news/risc-v-summit-2018-highlight-video-celebrates-a-banner-year/.]]>