Codasip. “They also want support for various low power modes.” This is particularly important for the RISC-V ISA, where quality concerns are popping up given that every physical implementation of RISC-V ISA is different. “RISC-V is merely an ISA spec, and it’s up to each provider to implement that ISA spec as they see fit,” Jones said. “The quality of RTL deliverables varies widely within the RISC-V community. Part of that is expected because part of these are academic contributed cores with limited support. But even a recently announced core that the developer [a fabless semiconductor company] patted itself on the back for open sourcing has a bug in the AXI bus.” To read more, please visit: https://semiengineering.com/why-ip-quality-is-so-difficult-to-determine/]]>