The RISC-V Privileged ISA specification, allows for controlling the core data endian (the order in which the data is stored in memory) at runtime, using bits in the STATUS register. However, it is not currently supported in any commercially available hardware or in emulators, such as QEMU. Since Codethink has a history of bringing big-endian support to traditionally little-endian processor architectures, a project to investigate the new bits on RISC-V was proposed.
There are still applications where the way data is stored matters, such as the protocols that move data across the Internet, which are defined as big-endian. So when a little-endian system needs to inspect or modify a network packet, it has to swap the big-endian values to little-endian and back, a process that can take as many as 10-20 instructions on a RISC-V target which doesn’t implement the Zbb extension.