Lauterbach is not only the global market leader in development tools for embedded systems; it has been part of the RISC-V community from the very beginning. In various working groups of the RISC-V Foundation, Lauterbach engineers have laid the foundations for developers around the world to build and use excellent RISC-V chips, CPU IP and applications.
By Frank Riemenschneider, Senior Marketing Expert, Lauterbach GmbH
For over 45 years, Lauterbach has been a trusted partner working alongside the world’s leading technology companies, enabling its embedded innovations for a smarter, more sustainable world.
Whether they’re building medical devices, vehicles, smartphones, renewable energy products or something else, these companies all have one thing in common: they trust the Lauterbach staff and TRACE32®, the World’s leading development tools.
As the technological landscape has changed and evolved, so has Lauterbach—fully embracing new initiatives. Of these, none is more worthy of celebration than the RISC-V architecture, characterized by its hallmark openness and flexibility. The growing influence of RISC-V is also a symbol of the drive for democratization and inclusivity of technology.
RISC-V was born exactly 15 years ago this week, at the University of California, Berkeley, by a team under the direction of David Patterson. In 2014, Professor Krste Asanović and Patterson published an article in which they argued that the future belongs to processors with a simplified instruction set architecture (ISA) that is distributed on an Open-source basis.
Lauterbach has been a member of the RISC-V community ever since.
Read more about the history of RISC-V here: High RISC, High Reward: RISC-V at 15
15 years after the project was launched, it can be seen that more and more semiconductor manufacturers are implementing RISC-V-based cores on their chips and the ecosystem is growing steadily. In this respect, the phrase “Happy Birthday RISC-V!” describes nothing but the truth: there is every reason to celebrate a very happy occasion.
From architecture to chip to application: Lauterbach as the key to success
Today, Lauterbach offers the broadest support for RISC-V based 32- and 64-bit chips – more than 100 – from various manufacturers[1]. This is not a matter of course, as RISC-V processors are also characterized by their modularity. This means that the architecture allows the creation of user-defined instruction sets so that developers can customize the processor for a specific application. This means that you don’t have to “pay” for instructions that you don’t use, which translates into resource savings and greater efficiency. But of course, these customized instruction sets must also be supported by development tools, which is something already proven in Lauterbach’s TRACE32® debuggers.
In 15 years of working with the RISC-V Foundation, chip manufacturers and their customers, Lauterbach has had numerous memorable RISC-V moments. A particular highlight was the RISC-V Summit in Barcelona in 2018, a kind of inflection point for the acceptance of RISC-V in the industry. For the first time, Lauterbach had many successful discussions with partners from the entire value chain who were clearly committed to RISC-V. At this summit, it became clear that Lauterbach would only be successful in the future with broad support for RISC-V. Strategic decisions were made, such as the expansion of the RISC-V development team and additional marketing measures together with the ecosystem partners. Today, in 2025, Lauterbach’s TRACE32® products for RISC-V are among the top-selling architectures in the company’s overall portfolio.
In addition to these obvious changes for Lauterbach, thanks to RISC-V, there have also been various internal advances. RISC-V has opened up the field of vision for new technologies, new partnerships have been formed and existing ones have been expanded.
Certainly, the most important contribution to the RISC-V community was made by Lauterbach engineers in various working groups dealing with the standardization of debug and trace interfaces for RISC-V chips. First, the “RISC-V External Debug Support” Specification v1.0.0 was adopted, which incorporates everything needed for simple and complex debugging scenarios. It’s a great solution for simple and fairly complex RISC-V systems and open to adaptions to support most complex and diverse SoCs[2].
Subsequently, the specifications for two RISC-V trace standards were adopted, the RISC-V E-Trace Standard and the RISC-V N-Trace standard. Both provide different optimization mechanisms and protocol characteristics. The latest RISC-V trace specifications are also suitable for heterogeneous systems and are supported by Lauterbach tools in various implementations.
Lauterbach’s contributions to these specifications made a big difference: Our inputs to the trace control interface have significantly led to its flexibility and comprehensibility. Beyond that, our experience with RISC-V users all over the globe triggered the development of the “Unformatted Trace & Diagnostic Data Packet Encapsulation for RISC-V” specification.
After 15 successful years of RISC-V, the question naturally arises as to what we can expect from the next 15 years. Well, there will be new chips from major and established manufacturers, and thanks to the comparatively low financial barrier to entry for start-ups, there will certainly be some surprises in chip design. Whether it’s decarbonization, further advances in medical technology for a healthier society, or artificial intelligence (AI) in safer cars for fewer injuries and deaths on the roads, RISC-V chips will play their part in making these dreams a reality.
With a growing ecosystem and even more collaboration in the embedded industry, Lauterbach will continue to play its important part in ensuring that in 2040 it will once again be “Happy Birthday, RISC-V!”