In 2010, a modest summer project at UC Berkeley sought a suitable instruction set architecture (ISA). Now, 15 years later, RISC-V is a global alternative to commercial chip architectures.
The team, led by Professor Krste Asanović and graduate students Andrew Waterman and Yunsup Lee, with pivotal support from Professor David Patterson, felt existing ISAs suffered from “baggage” and that “Moore’s Law was slowing and Dennard Scaling was ending, requiring specialization, customization, and parallelism.”