RISC-V Ecosystem News

SiFive Advances Custom Silicon Industry with New Partnerships, Products at 7th RISC-V Workshop

At the 7th RISC-V Workshop today, SiFive, the first fabless provider of customized, open-source-enabled semiconductors, announced a number of new partnerships and products that exemplify the company’s rapid growth over the past year. These announcements provide further proof of SiFive’s leadership in aligning with industry leaders to spur innovation in the plateauing semiconductor industry as well as the company’s ability to meet increased demand for open access to custom silicon. The…

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SiFive Joins FDXcelerator Program to Bring RISC-V Core IP to GLOBALFOUNDRIES’ 22FDX Process Technology

SiFive announced today that it has joined GLOBALFOUNDRIES’ FDXcelerator™ Partner Program, and will be making RISC-V CPU IP including SiFive’s E31 and E51 RISC-V cores available on GF’s 22FDX® process technology. Based on the open source RISC-V ISA, the SiFive E31 offers embedded chip designers new capabilities in high performance within strict area and power requirements, and the SiFive E51 offers a full 64-bit performance at 32-bit price, power and area.https://www.sifive.com/posts/2017/11/28/sifive-joins-fdxcelerator-program-to-bring-risc-v-core-ip-to-globalfoundries-22fdx-process-technology/ 

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Reduced Energy Microsystems Joins RISC-V Foundation

Reduced Energy Microsystems (REM), a semiconductor startup working on ultra-low power SoCs for embedded vision, announced today that it has joined the RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the open, free RISC-V instruction set architecture (ISA) forward.http://www.prweb.com/releases/2017/11/prweb14950212.htm

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Renode 1.2 With RISC-V Support To Be Presented At 7th RISC-V Workshop

Building on the great momentum behind Antmicro’s open source multinode simulation framework, and in preparation for the 7th RISC-V Workshop happening in Milpitas, CA this week, Antmicro has just announced the release of Renode 1.2 – a landmark moment for the project that introduces official support for the acclaimed RISC-V architecture.http://antmicro.com/blog/2017/11/renode-1-2-at-7th-risc-v-workshop/

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SiFive and Microsemi Expand Relationship with Strategic Roadmap Alignment and a Linux-Capable, RISC-V Development Board

SiFive, the first fabless provider of customized, open-source-enabled semiconductors, and Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, at the 7th RISC-V Workshop today announced the companies have formed a strategic relationship to meet the growing interest and demand in the RISC-V instruction set architecture. The companies have previously collaborated to provide RISC-V soft CPU cores for Microsemi’s PolarFire® FPGAs, IGLOO™2 FPGAs,…

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Codasip Announces Bk5-64, A New 64-Bit RISC-V Processor

Codasip, the leading supplier of RISC-V® embedded processor IP, today announced that it has expanded its Berkelium processor portfolio to include the Bk5-64, its first implementation of the 64-bit RISC-V ISA. Codasip now offers customers the broadest selection of RISC-V processors in the market, spanning from the ultra-low-power zero-stage Bk1 to the high-data-bandwidth, energy-efficient Bk5-64. All Berkelium processors are generated via the unique Codasip Studio customization tool, allowing for fast configuration and optimization…

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SEGGER Embedded Studio Supports RISC-V Architecture

SEGGER Microcontroller announces the new RISC-V edition of its market leading multi-platform Embedded Studio integrated development environment (IDE). SEGGER Embedded Studio is the first professional IDE which supports the open source RISC-V CPU architecture. Embedded Studio for RISC-V comes with the same features and benefits of Embedded Studio for Arm and Cortex-M and makes it painless for users to transition between both architectures. Embedded Studio for RISC-V makes it very easy to evaluate…

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Andes Announces Advanced SoC Development Environments for V5 AndesCore N25 and NX25 Processors with Tool Partners

Andes Technology Corporation, the leading Asia-based supplier of compact, low-power, high-performance 32/64-bit embedded CPU cores and a founding member of RISC-V Foundation, today announces the partnership with the world-class tools vendors including Imperas, Lauterbach, Mentor, a Siemens Business, and UltraSoC (in alphabetical order) to bring their system-on-chip (SoC) development environments to Andes V5 processors and the RISC-V community.http://www.marketwired.com/press-release/andes-announces-advanced-soc-development-environments-v5-andescore-n25-nx25-processors-twse-6533-2241238.htm

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Andes and Imperas Partner to Deliver Models and Virtual Platforms for Andes RISC-V Cores

Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, and Andes Technology Corporation, today announced their partnership to provide Open Virtual Platforms (OVP) models, virtual platforms and software solutions for Andes next-generation processors, based on the RISC-V architecture.http://www.imperas.com/articles/andes-and-imperas-partner-to-deliver-models-and-virtual-platforms-for-andes-risc-v-cores

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Embedded Tools Provider Ashling Joins RISC-V Foundation

Ashling Microsystems Limited, a leading supplier of high-performance embedded software and hardware tools, today announced that it has joined the RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the open, free RISC-V instruction set architecture (ISA) forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the…

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