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RVfpga (RISC-V fpga) Understanding Computer Architecture Workshop-May 20th&21st

April 4, 2022 @ 8:00 am - 5:00 pm PDT

Teaching Computer Architecture? Give us a day of your time, and we will set you up to teach with RISC-V, the fastest growing new ISA

About this event

 RVfpga (RISC-V fpga) Understanding Computer Architecture Workshop-May 20th image

RVfpga (RISC-V fpga) Understanding Computer Architecture – A Hands-On, In-Person, One-Day-Workshop

Bring RISC-V to your course in computer architecture using RVfpga

This workshop shows how to use RISC-V to teach computer architecture and the design of systems on chip (SoCs). Let us empower you to teach next generation computer science, electrical and computer engineering students with hands-on real-world expertise in computer architecture and the RISC-V instruction set architecture.


What is the RVfpga workshop about?

RISC-V is a rapidly growing world-wide movement. It is open source and provides extensions, making it easier to target to various platforms. This RVfpga workshop presents a commercial RISC-V system targeted to an FPGA, discusses the theory, architecture, and course structure, and shows how to use the hands-on labs that are provided as part of the complete RISC-V FPGA (RVfpga) Course. The course explores the fundamentals of computer architecture using Western Digital’s open-source, commercial SweRV EH1 RISC-V core targeted to a Xilinx Artix 7 FPGA on Digilent’s Nexys A7 development board. Everyone will get hands-on experience with this FPGA platform and the software tools, enabling a fast start when you return to your university.


What will you learn?

The workshop shows how to quickly get the RISC-V FPGA system and RISC-V tools up and running. Then, we describe all of the RVfpga labs and show how to use and work through a selection of the labs hands-on. We also discuss how to integrate RVfpga into your curriculum.

Specific topics include:

* Installing tools (which can be done before the workshop)

* Targeting the SweRV EH1 RISC-V core and SoC to an FPGA

* Programming the RISC-V SoC

* Adding more functionality to the RISC-V SoC

* Analyzing and modifying the RISC-V-core and memory hierarchy


Workshop Schedule: 9AM to 5PM


Draft Schedule:

– Welcome, Introductions and Set-up

– Digi-Key’s Academic Programme

– Introduction to the teaching materials and workshop


– Instruction and Hands-On Labs

– Overview of the Imagination University Programme

>> Lunch Break and Networking

– Instruction and Hands-On Labs

– Feedback Forms


– How to fit RVfpga into your curriculum, Your next steps, Q&A


*The schedule for the day is subject to change. So that you can plan your travel, we will not start earlier than 9AM and our finish will be 5PM latest.

– Hotel recommendations and logistics information will be provided.



UNLV is not far from the world famous “strip” and only about 20 minutes by Uber from Las Vegas (LAS) airport.

Building: TBE-B, Room: 348



All delegates will be given access to the lecture slides and course notes, programming exercises and solutions as well as example exam questions and answers.


Note: TWO One-Day Workshops!

There are 2 consecutive one-day workshops on May 20th and 21st at UNLV, please choose the one that suits you the best!

May 20th registration:


May 21st registration:


For more information about the Imagination University Programme and RVfpga CLICK HERE.


Workshop Trainer:

Dr. Sarah Harris, professor of electrical and computer engineering at the University of Nevada, Las Vegas. Sarah Harris earned her M.S. and Ph.D. at Stanford University. She is the co-author of three popular textbooks: Digital Design and Computer Architecture, 2nd Edition (2007), ARM Edition (2015), and RISC-V Edition (2021). Her research interests include computer architecture and applications of embedded systems and machine learning to biomedical engineering and robotics.

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