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The 26th Asia and South Pacific Design Automation Conference Technical Program

January 8, 2021 @ 8:00 am - 5:00 pm PST

ASP-DAC is the largest conference in Asia and South-Pacific regions on Electronic Design Automation (EDA) area for VLSI and systems. ASP-DAC has been started at 1995 and this ASP-DAC 2021 is 26th conference. ASP-DAC 2021 offers you an ideal opportunity to touch the recent technologies and the future directions on the LSI design and design automation areas by technical papers and tutorials. ASP-DAC also holds Designers’ Forum to make presentations about the latest designs for designers.

RISC-V Content

Session 1D Validation and Verification
Time: 15:00 – 15:30, Tuesday, January 19, 2021

Mutation-based Compliance Testing for RISC-V
Author: Vladimir Herdt (DFKI GmbH, Germany), *Sören Tempel (Univ. of Bremen, Germany), Daniel Große (Johannes Kepler Univ. Linz, Austria), Rolf Drechsler (Univ. of Bremen & DFKI GmbH, Germany)

Compliance testing for RISC-V is very important. Essentially, it ensures that compatibility is maintained between RISC-V implementations and the ever growing RISC-V ecosystem. Therefore, an official compliance testsuite is being actively developed. However, it is very difficult to achieve that all relevant functional behavior is comprehensively tested. In this paper we propose a mutation-based approach to boost RISC-V compliance testing by providing more comprehensive testing results. Therefore, we define mutation classes tailored for RISC-V to access the quality of the compliance testsuite and provide a symbolic execution framework to generate new testcases that kill the undetected mutants. Our experimental results demonstrate the effectiveness of our approach. We identified several serious gaps in the compliance testsuite and generated new tests to close these gaps.


Session 3E Timing Analysis and Timing-Aware Design
Time: 16:00 – 16:30, Tuesday, January 19, 2021

Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization
Author: TaiYu Cheng (Osaka University, Japan), Yutaka Masuda (Nagoya University, Japan), Jun Nagayama, Yoichi Momiyama (Socionext Inc., Japan), Jun Chen, Masanori Hashimoto (Osaka University, Japan)

This paper proposes a design optimization methodology that can achieve a mode-wise voltage scalable(MWVS) design with applying the activation-aware slack assignment (ASA). Originally, ASA allocates the timing margin of critical paths with the stochastic treatment of timing errors, which limits its application. Instead, this work employs ASA with guaranteeing no timing errors. The MWVS design is formulated as an optimization problem that minimizes the overall power consumption considering each mode duration, achievable voltage reduction, and accompanied circuit overhead explicitly, and explores the solution space with the downhill simplex algorithm that does not require numerical derivation. For obtaining a solution, i.e., a design, in the optimization process, we exploit the multi-corner multi-mode design flow in a commercial tool for performing mode-wise ASA with sets of false paths dedicated to individual modes. Experimental results based on RISC-V design show that the proposed methodology saves 20% more power compared to the conventional voltage scaling approach and attains 15% gain from the single-mode ASA. Also, the cycle-by-cycle fine-grained false path identification reduced leakage power by 42%.


Session 4B System-Level Modeling, Simulations, and Exploration
Time: 15:00 – 15:30, Wednesday, January 20, 2021

Arbitrary and Variable Precision Floating Point Arithmetic Support in Dynamic Binary Translation
Author: Marie Badaroux, Frédéric Pétrot (Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, France)

Floating point hardware support has more or less been settled 35 years ago by the adoption of the IEEE 754 standard. However, many scientific applications require higher accuracy than what can be represented on 64 bits, and to that end make use of dedicated arbitrary precision software libraries. To reach a good performance/accuracy trade-off, developers use variable precision, requiring e.g. more accuracy as the computation progresses. Hardware accelerators for this kind of computations do not exist yet, and independently of the actual quality of the underlying arithmetic computations, defining the right instruction set architecture, memory representations, etc, for them is a challenging task. We investigate in this paper the support for arbitrary and variable precision arithmetic in a dynamic binary translator, to help gaining a system level view of what such an accelerator could provide as interface to compilers, and thus programmers. We detail our design and present an implementation in QEMU using the MPRF library for the RISC-V processor.


January 8, 2021
8:00 am - 5:00 pm PST
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